Asymmetric routing in 3D NoC using interleaved edge routers

Abstract

Network on Chip (NoC) concept has evolved as a standard design approach for integrating large number of processing cores within a single die. The performance improvements which occur due to topological optimizations and architectural enhancements of NoCs can be remarkably increased by the adoption of 3D IC fabrication technology. However, conventional 3D NoC architecture designs are significantly affected by router area and power dissipation issues when compared with traditional 2D NoCs. Also, 3D NoC utilizes considerable number of Through Silicon Vias (TSVs) which raises area overhead leading to minimal yield and wafer utilization. In this paper, we propose an asymmetric routing approach in bufferless 3D NoC using interleaved edge routers for enhancing NoC performance. Simulation results show that our proposed M-3D (Modified Three Dimensional) mesh design has better throughput, lower average flit latency and deflection rate compared to state-of-the-art bufferless networks, employing same number of routers.