On-chip Global Interconnects Research Articles

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

Design and performance analysis of buffer inserted on-chip global nano interconnects in VDSM technologies

A methodology for the SPICE-Compatible modelling of metal-semiconductor-metal photodetectors for nanophotonic interconnects application

On-chip global nanophotonic interconnects are promising alternatives to traditional metallic interconnects in giga-scale integrated circuits. At the very first step, the design and optimization of nanophotonic interconnects require the modelling and characterization of optoelectronic devices with irregular 3D geometries. In this paper, a methodology for the SPICE-compatible modelling of such devices is proposed which does not rely on post-manufacturing data. This methodology couples the optics and electronics domains of such devices in order to improve the model accuracy. The proposed methodology has been applied to the modelling of a waveguide-coupled integrated Metal-Semiconductor-Metal PhotoDetector (MSM PD) with quadratic nanotapers. We have performed optics domain simulation in 3D field-solver MEEP and device simulations using Silvaco Atlas device-TCAD tool. The simulation results agree well with measurement data reported in literature. Agreement with less than 12% error at all bias voltages is observed.

Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects

The full-duplex data communication over on-chip global interconnects suffers from large amounts of amplitude residue echo, leading to the closure of the vertical eye. This work proposes, a residue monitor enabled adaptive echo-cancellation scheme for full-duplex communication with power efficient charge-mode circuits. The proposed architecture employs charge-domain echo cancellation scheme for separating the outbound signal from the inbound signal by precisely controlling the capacitor bank output, thanks to the availability of residue monitor and high precision MOS switches and capacitors at sub-100 nm technology nodes. The residue monitor in the loop tracks the amount of amplitude residue and then sets the control bits, when the loop is locked. Further, this work proposes power efficient charge-mode circuits based replica generation stage, which does not contribute to additional power consumption like in the conventional echo-cancellation schemes. The proposed scheme is implemented at the architectural level with behavioural modeling in Verilog-AMS and also at the circuit level in 1.2 ​V, 65-nm CMOS Technology. The behavioural simulations shows that the residue monitor loop is getting locked while tracking the control voltage generated by the charge regulator for the target near-zero amplitude residue and accordingly control bits to the capacitor bank are set. Circuit level performance shows the functioning at a bidirectional data rate of 20 Gbps over a 1-mm on-chip global interconnect and the extracted received signal has 149 ​mV differential swing at a power consumption of 9.64 ​mW.

Hybrid bidirectional transceiver for multipoint‐to‐multipoint signalling across on‐chip global interconnects

The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link. Also, compared to existing passive terminated interconnect with current-mode receivers at all the points, the proposed link deploys low impedance current-mode receivers providing active terminations at both the ends of the interconnect and high-impedance voltage-mode receivers, which do not consume any portion of the signalling current, at the intermediate nodes of the interconnect which further lowers the required transmitter signalling current. A mixed-mode or hybrid transceiver architecture has been proposed for the aforementioned link, which can act either as a current-mode transmitter or a current-mode receiver or a voltage-mode receiver. The architecture has been implemented in 0.18-μm complementary metal oxide semiconductor technology for an interconnect of length 4 mm and having five transceiver nodes. The total energy efficiency of the architecture is 0.70 pJ/b for a speed of 3.0 Gb/s.

Analyzing Crosstalk-Induced Effects in Rough On-Chip Copper Interconnects

Aggressive scaling of on-chip interconnects results in significantly higher coupling capacitance, which results in crosstalk effects as we enter the end-of-the-roadmap era. Moreover, surface roughness is seen as a major contributor to conductor losses that further exacerbates these crosstalk-induced effects. This article reports an exhaustive analysis of crosstalk-induced effects, considering interconnect surface roughness at current and future technology nodes (i.e., 13 and 7 nm), for on-chip global copper interconnects. The role of repeater insertion in rough interconnects is also presented in our work. For our analysis, we have used an aggressor-victim-aggressor three-line bus architecture and FINFET-based driver circuits with binary input logic. Our results show that surface roughness degrades typical interconnect performance metrics i.e., worst case delay, bandwidth density (BWD), power consumption, and power-delay product. At a 7-nm technology node, average worst case crosstalk delay and power consumption increase by 17× and 9×, respectively, when compared to smooth interconnects. Similarly, due to surface roughness, BWD reduces by nearly 17× for 7-nm global interconnects. For data rates of 0.2 Mb/s, eye height and eye width are reduced by 73% and 54%, respectively, in the worst case scenario for 7-nm global lines. Finally, we showcase the role of repeater insertion in enhancing performance metrics, in which crosstalk delay and power delay products are significantly improved (by 85% and 99%, respectively) at a 7-nm technology node.

Packaging Renaissance with Chiplets

Abstract With ever shrinking advanced CMOS nodes and evolution of systems with increasing complexity, the traditional SoC paradigm is facing extensive challenges in terms of yields and heterogeneity. The emerging industry solution to this has been to partition the SoCs into smaller units, with each unit performing a certain (though exclusive) function. This drove the birth of “chiplets”. With advent of chiplets, the traditional function of packaging as an after-thought to chip development has got a revolutionary face-lift. Packaging is now enabling interconnects to replace on-chip global interconnects. The onus now is on packaging to get the chiplets to integrate and communicate with each other such that the net performance is equivalent to or better than SoC. This has spawned a renaissance in field of semiconductor packaging, with newer multi-die packaging technologies being productized to realize newer and better interconnects. Some examples of these emerging technologies include advanced flip-chip, 2.5D, 2.1D, 3D, Wafer Level Fan-Out, and Bridge Technologies. AMD is at forefront of chiplet technologies, with extensive 7nm chiplet based product portfolio catering to the HPC market. This talk will discuss the current state of chiplet packaging technologies.

An energy-efficient multi-level RF-interconnect for global network-on-chip communication

A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) using a sub-harmonic multiply-by-10 injection-locked frequency multiplier is also designed to support a fully-synchronous NoC architecture. A differential voltage-controlled oscillator (VCO) used in a PLL creates an output frequency for a frequency range between 0.5 and 2.65 GHz signal. The multiply-by-10 ILFM generates 10 times higher frequency than the VCO output signal. Using the proposed multiply-by-10 ILFM can minimize the number of power-hungry frequency divider stages in a PLL feedback loop, resulting in improvement of the MRI power efficiency. The MLS-based BB and ASK-based RF band carry 10 Gb/s/pin and 4.4 Gb/s/pin, respectively. The proposed system is fabricated in a 65 nm CMOS process and achieves an energy efficiency of 2 pJ/b.

Investigation of Copper–Carbon Nanotube Composites as Global VLSI Interconnects

Applicability of copper–carbon nanotube (Cu-CNT) composites as on-chip global VLSI interconnects is investigated comprehensively. Electrical modeling of Cu-CNT composite interconnects is carried out by virtue of effective complex conductivity. The performances, including time delay and step response, are characterized based on the equivalent circuit model. Finally, the crosstalk effect between coupled Cu-CNT composite interconnects is analyzed.

Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects

This paper presents a current-mode triline ternary-level coded differential signaling scheme for high-speed data transmission across on-chip global interconnects. An energy efficient current-mode triline transceiver pair suitable for this signaling scheme has been proposed. Compared with a voltage mode receiver with resistive termination, the proposed active terminated current-mode receiver reduces the signal current by 7.8 times and the signaling power by 2.6 times. Two data transmission schemes are proposed for using this transceiver pair. In the first scheme, two data streams are directly transmitted over the three lines link, thereby having a wire efficiency of 67%. In the second scheme, five data streams at half rate are encoded and serialized to send over the three lines, thereby having a wire efficiency of 83%. A prototype design has been implemented in a UMC 0.18- $\mu \text{m}$ technology for an interconnect of length 5 mm. The measured energy efficiency of the triline transceiver in a direct transmission scheme for the data rate of 7.4 Gb/s is 0.61 pJ/bit. With the encoding scheme, the energy efficiency is 1.24 pJ/bit for a total data transmission of 9.25 Gb/s.

Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects

This paper presents an energy efficient full-duplex (FD) current-mode transceiver for on-chip global interconnects. As it shares the same signaling port for transmitting and receiving signal, the wire efficiency is increased by $2\times $ compared to unidirectional transceivers. The proposed hybrid transceiver has a directional inverter/buffer (DIB) circuit which inverts the outbound signal whereas conveys the incoming signal maintaining the same phase with a gain greater than one. As a result, the incoming signal is seamlessly separated from the strong outbound signal just by weighted addition of the two compound signals on the either sides of the DIB by a transconductor (gm) circuit. This is in contrast to existing subtraction based signal dissociation architecture. Importantly, the inbound signal retrieval process is a constructive one where the two components of the incoming signal are added up to provide inherent gain, making it suitable for lossy on-chip link. Moreover, the DIB circuit has very low active impedance at its input/output node and hence supports high bandwidth transmission without using any passive terminator. A prototype design has been implemented in 0.18- $\mu \text{m}$ CMOS process for a global interconnect of 5 mm length. Measured results give an efficiency of 0.19 pJ/b/mm for an FD operation of 4.0 Gb/s.

Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System

ABSTRACTCurrent-mode signalling scheme is one of the prominent solutions for high-speed and high data rate communication in global on-chip interconnects. Advancements in nanofabrication processes and housing of billions of transistors on a single silicon chip have made process-induced variations in transistors and interconnects quite significant. Analysis of parameter variations has become an important step in predicting the reliability and addressing various electronic circuit design issues in nanoscale regimes. The present paper evaluates the stochastic parameters variability on the electrical performance of on-chip current-mode interconnect system. Both transistor and interconnect variability effects are analyzed. Interconnect is modelled by an equivalent distributed line model and is driven by a current-mode driver. The impact of variability is assessed via parametric, process corner and Monte–Carlo analyses. The variability analysis is carried out for single as well as coupled 2-Line, 3-Line and 5-Line interconnect structures. Furthermore, the impact of individual process parameter variability in current-mode interconnect system has been investigated using statistical techniques namely Taguchi design of simulation scheme, ANOVA and Rank table.

High-speed low-power on-chip global interconnects using low-swing self-timed regenerators

In this paper, we present a mixed design of Low-Swing scheme and Self-Timed Regenerator (LS-STR). Our novel design reduces the energy-delay product (EDP) and eliminates one of the fabrication constraints resulting from multi-threshold transistors employed. Therefore, it is suitable for long global on-chip interconnects. We have simulated our design using CMOS 90-nm technology at 1.0V power supply, to transmit signal along a 10-mm interconnect line. Our simulation results for different wire widths reveal that the propagation time delay is reduced by 39.1% for iso-power compared with that of the optimal repeater insertion case. Also, up to 23.2% power reduction is achieved for iso-delay mode. Moreover, we have compared our scheme against Self-Timed Regenerator (STR) scheme along all wire widths. Our results show power consumption and delay time reduction of 21.4% and 12.1% for iso-delay and iso-power modes, respectively. The time delay improvement is up to 15.1% in the best case. Furthermore, PVT variation simulation shows that the LS-STR has more tolerance to the parameter variations with respect to the STR design due to avoiding use of multi-threshold transistors in the LS-STR design. Moreover, we have analyzed the reliability of the circuit, considering process and power supply rail variations and inter-line crosstalk noise. The LS-STR improves the Signal to Noise Ratio (SNR) by 3.7% compared with the STR design. The key advantage of our LS-STR scheme is that there is no need for multiple-threshold process technology or an extra power supply rail.

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects

On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3[Formula: see text]dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10[Formula: see text]mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.

High‐speed energy‐efficient bi‐directional transceiver for on‐chip global interconnects

In this paper, a new bi-directional transceiver has been proposed for high-speed signalling across on-chip global interconnects. The proposed transceiver has two modes of operation namely, the transmitter and the receiver. As a result, two transceivers sitting at the two ends of an interconnect can support two-way communication through the same link. The transceiver has very low small-signal impedance for both modes of operation and thereby supports high bandwidth of the link. Moreover, because of its high transimpedance gain over a large bandwidth in the receiving mode, the signalling current can be reduced to a very low value. The circuit has been designed in 65 nm, 1.2 V process with a global interconnect of length 10 mm and width 1.5 μm. Post-layout simulation of the transceivers with the link gives an energy efficiency of 0.101 pJ/b for a data transmission of 14 Gbps.

Design optimization for capacitive-resistively driven on-chip global interconnect

Design optimization for capacitive-resistively driven on-chip global interconnect

Performance Analysis of Alternate Repeaters for On-Chip Interconnections in Nanometer Technologies

As the geometries of integrated circuits continue to shrink into the deep nanometer regime, the impact of on-chip interconnects is dominant on the overall system performance. This paper explores the power-delay trade-off in alternate repeater insertion techniques. The repeaters are placed along global on-chip interconnects to compensate the loss in the wires and to regenerate the signal strength. All the repeater insertion techniques with 3-pi RC distributed interconnect model are implemented at 45nm and 180nm technology with supply voltage operated at 1GHz. The performance metrics considered to compare the alternate repeated interconnects are power dissipation, propagation delay and power-delay-product (PDP).

Current-Mode Transceiver for Silicon Interposer Channel

An energy-efficient 3 Gb/s current-mode interface scheme is proposed for on-chip global interconnects and silicon interposer channels. The transceiver core consists of an open-drain transmitter with one-tap pre-emphasis and a current sense amplifier load as the receiver. The current sense amplifier load is formed by stacking a PMOS diode stage and a cross-coupled NMOS stage, providing an optimum current-mode receiver without any bias current. The proposed scheme is verified with two cases of transceivers implemented in 65 nm CMOS. A 10 mm point-to-point data-only channel shows an energy efficiency of 9.5 fJ/b/mm, and a 20 mm four-drop source-synchronous link achieves 29.4 fJ/b/mm including clock and data channels.

A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18μm CMOS process to test the topology with a prototype global interconnect having a length of 10mm. Power consumption of the transceiver for a data rate of 2.5Gbps data is 2mW. This gives an energy efficiency of 0.8pJ/b.

Thermal sensitivity analysis of on‐chip interconnects

A new method for time-domain sensitivity analysis of on-chip coupled interconnects with non-uniform substrate temperature profiles is presented. The parametric macromodelling is performed via multivariate rational approximation using magnitude vector fitting algorithms. The waveform relaxation algorithm with transverse partitioning is employed for efficient sensitivity analysis of coupled interconnects. With these techniques, the thermal sensitivity of on-chip global interconnects arising from typical substrate thermal profiles are investigated.

Review of Electromagnetic failure, optimization techniques and stress prediction in Interconnect

The ever increasing demand of digital computing and wireless communication have been driving the semiconductor technology to change with passing days. Modern electronics system integrates more complex component and devices, which result in a very complex electromagnetic field environment Moore’s law has driven the scaling of digital electronic devices, dimensions and performances over the last 40 years. In today’s world, there is demand of devices which are faster, better and having less power consumption. Now we need to better optimize the circuit at available technologies. Interconnection used to connect components on a VLSI chip, chips on a multichip module and to connect multichip modules on a system board. Most of the chips are covered by Interconnects. On-chip interconnects which was considered only as a parasitic load before 1990s became the real performance bottleneck due to its extremely reduced cross section dimension [31]. Today, onchip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, higher power dissipation and limited bandwidth.