On-chip Global Interconnects Research Articles

Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects

Nonuniform thermal profiles on the substrate in high-performance ICs can significantly impact the performance of global on-chip interconnects. This paper presents a detailed modeling and analysis of the interconnect performance degradation due to the nonuniform temperature profiles that are encountered along long metal interconnects as a result of existing thermal gradients in the underlying Silicon substrate. A nonuniform temperature-dependent distributed RC interconnect delay model is proposed. The model is applied to a wide variety of interconnect layouts and substrate temperature distributions to quantify the impact of such thermal nonuniformities on signal integrity issues including speed degradation in global interconnect lines and skew fluctuations in clock signal distribution networks. Subsequently, a new thermally dependent zero-skew clock-routing methodology is presented. This study suggests that thermally aware analysis should become an integrated part of the various optimization steps in physical-synthesis flow to improve the performance and integrity of signals in global ultra large scale integration interconnects.

Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling

This paper discusses performance limitation of on-chip interconnects. On-chip global interconnects are considered to be a bottleneck of high-performance LSIs. To overcome this issue, high-speed signaling and large throughput interconnection using electrical wires have been studied. However the limitation of on-chip interconnects has not been examined sufficiently. This paper reveals the maximum performance of on-chip global interconnects based on derived analytic expressions and detailed circuit simulation. We derive trade-off curves among bit rate, interconnect length, and eye opening both for single-end and for differential signaling. The results show that differential signaling improves signaling performance several times compared with conventional single-end signaling, and demonstrate that 80 Gbps differential signaling on 10 mm interconnects is promising.

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

On-chip global interconnect exhibits clear frequency dependence in both resistance (R) and inductance ( L). In this paper, its impact on modern digital and radio frequency (RF) circuit design is examined. First, a physical and compact ladder circuit model is developed to capture this behavior, which only employs frequency independent R and L elements, and thus, supports transient analysis. Using this new model we demonstrate that the use of dc values for R and L is sufficient for timing analysis (i.e., 50% delay and slew rate) in digital designs. However, RL frequency dependence is critical for the analysis of signal integrity, shield line insertion, power supply stability, and RF inductor performance.

Comparison between electrical and optical global clock distributions for CMOS integrated circuits

CMOS technology downscaling is expected to encounter a metallic interconnect bottleneck in the near future due to increasing delays of global on-chip interconnects, signal distortion, and timing uncertainty (skew and jitter), as well as power consumption. Silicon-compatible integration of optical on-chip interconnects is presented as an alternative solution. Integrated optics using silicon-on-insulator single-mode waveguides, Si-based modulators, and Ge photodetectors offers a feasible way to distribute the global clock over the whole chip. Taking into account the photodetectors' characteristics, with a CMOS-inverter-based transimpedance front-end amplifier and additional gain stages to ensure sufficient voltage swing, the performance of optical global clock distributions is compared with that of their metallic counterparts. The main advantages brought by optics include signal propagation with negligible distortion over centimeter-long distances (pulse spreading <1% of the clock period at a frequency of 100 GHz), reduction of skew and jitter in comparison with electrical repeater lines (optical skew/jitter <3% to 4% at a frequency of 50 GHz), lower sensitivity to temperature variations (optical delay variation <1.8% for a 100-K variation), and reduction of the total chip power consumption (negligible power consumption for the global clock distribution: <70 mW).

A Multiconductor Transmission Line Methodology for Global On-Chip Interconnect Modeling and Analysis

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists.