A low impedance receiver for power efficient current mode signalling across on-chip global interconnects

Abstract

In this work we propose a low impedance receiver for on-chip high speed current-mode signalling over global interconnect. The receiver provides a very low input impedance even with a low quiescent power. The low input impedance helps to get high link bandwidth without any passive terminator. Moreover, the receiver has high transimpedance gain over a large bandwidth. This facilitates in reducing the signalling current by 6.7 times compared to a passive termination. A test chip has been fabricated in 0.18μm CMOS process to test the topology with a prototype global interconnect having a length of 10mm. Power consumption of the transceiver for a data rate of 2.5Gbps data is 2mW. This gives an energy efficiency of 0.8pJ/b.