Off-state Bias Research Articles

Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs

Experimental and Numerical Analysis of Off-State Bias Induced Instabilities in Vertical GaN-on-Si Trench MOSFETs

Multi-functional metasurface as a transmissive/reflective FSS and an on-air frequency mixer

In this paper, a multi-functional metasurface is proposed, which can work as a narrowband transmissive/reflective frequency selective surface (FSS) and an on-air frequency mixer based on its switching response. The metasurface is made up of unit cells with square and circular metallic loops connected by PIN diodes controlled by a bias source. In contrast to typical wideband FSSs, the structure provides 0.55 GHz of narrow stopband (a fractional bandwidth of 22%) at 2 GHz in the OFF state bias. The bandstop response can be adjusted by varying the reverse bias voltage. The metasurface alternates between its functionalities when in forward bias by providing a passband at the operational frequency. The structure is compact and operates as a transmissive/reflective surface under two different bias conditions (ON and OFF). The design is angularly stable and polarization-insensitive for both TE and TM polarisation. A prototype of the designed structure is developed and the measured results correlate well with the simulated responses from the finite-difference time-domain (FDTD) method-based simulation of the circuit model. On-air frequency mixing for a wave propagating through the metasurface is demonstrated and the effects of different parameters affecting the mixing are parametrically studied through FDTD simulations and experiments.

High-Temperature Static and Dynamic Characteristics of 4.2-kV GaN Super-Heterojunction p-n Diodes

This article presents the static and dynamic characterization of 4.2-kV super-junction p-n diodes at high temperatures. Reduction of the forward current with increasing temperature is consistent with 2DEG mobility degradation caused by polar optical phonon scattering. Reverse leakage current was dominated by isolation leakage, with an activation energy of ~0.26 eV, close to the reported activation energy of surface leakage. Dynamic switching characterization in the temperature range from room temperature (RT) to 300 °C showed a nonmonotonic dependence of dynamic ON-resistance on temperature. At room temperature and 50 °C, devices showed zero current collapse (CC) up to OFF-state stress bias of 3 kV at 100 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> timescale. Between 100 °C and 200 °C, significant CC was observed. From 250 °C to 300 °C, devices showed recovery from the severe CC. The degradation and recovery of dynamic ON-resistance can be explained by emission and recapture of holes during the OFF- and ON-states, respectively.

Integrated GaN HEMT Cascode Power Module Stability Analysis under Negative Gate Bias Stress for Power Electronic Applications

We present a detailed investigation of two forms of negative gate bias stress in four parallel GaN HEMTs in cascode configuration in this article: (i) pulsed off-state gate bias and (ii) negative bias temperature instability (NBTI). Device statical parameter degradations and instabilities, such as IDS, RDS-ON, GM, max, and IGSS, are evident under low/mid pulsed off-state gate bias stress conditions, according to the measured results of pulsed gate bias stress. Under NBTI experiments, mid/high off-state bias stress with accelerated temperatures, the device demonstrated their excellent stability and negligible degradation of VTH and RDS-ON. These findings pave the way for evaluating device reliability and understanding the failure mechanism caused by negative gate bias stress, allowing emerging GaN cascode technologies to advance faster.

Vertical field inhomogeneity associated with threading dislocations in GaN high electron mobility transistor epitaxial stacks

A measurement technique combining Kelvin-probe force microscopy with substrate bias is developed and demonstrated on AlGaN/GaN-on-Si device structures under conditions relevant to the effect of off-state drain bias stress in transistors. For a high substrate bias, the measurements show a significantly lowered surface potential surrounding a small proportion of dislocations imaged with atomic force microscopy (AFM), laterally extending on a scale of up to a micrometer. Both the density and the size of those features increase with substrate bias; however, conductive AFM measurements under the same bias conditions showed no leakage reaching the surface associated with those features. Our model considers localized conductive paths that end a certain distance below the 2D electron gas electrically “thinning” the epitaxy and, therefore, deforming the potential and increasing the electric field under off-state stress bias. The conclusion is that the vertical electric field in the buffer is laterally highly non-uniform with an enhanced vertical field in the vicinity of those dislocations. This non-uniformity redirects the substrate bias stress from the buffer to the channel with potential consequences for breakdown.

(Invited) Processes and Characteristics of 10-Kv-Class GaN Super-Heterojunction Diodes

GaN power switches have demonstrated proven performance benefits in below 1200V applications. Scaling the GaN power devices to higher voltage will bring the performances benefits to high power systems, such as the electric grid. One technical challenging in upscaling the voltage is the E-field nonuniformity in GaN devices. The author's group has attempted to achieve uniform E-field and to upscale the breakdown voltage of GaN devices, using a charge-balanced super-heterojunction structure. GaN Schottky diodes with over 10 kV breakdown voltage have been demonstrated. These devices showed no degradation of dynamic on-resistance up to 3 kV off-state bias stress. This talk will report design, processes, and characteristics of the GaN super-heterojunction devices.

Review on the degradation of GaN-based lateral power transistors

Several mechanisms may contribute to the degradation of GaN transistors; in this paper we discuss the main processes that limit the lifetime of GaN power devices, with focus on the following relevant aspects: (i) the degradation/breakdown induced by off-state bias; (ii) the origin of vertical leakage and breakdown; (iii) the failure of the gate stack in MIS-HEMTs and in transistors with p-type gate. The data reviewed in this paper help the reader understanding the main issues related to the development of GaN-based transistors, and give hints on possible strategies to improve device reliability. The signatures of the main deep levels in gallium nitride, which can influence the reliability of the devices, are critically reviewed and summarized.

Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

New Degradation Model of LTPs TFT Aged Off-State Bias Stress on Flexible Substrate

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented a new degradation model using TCAD simulation. In the off-state bias stress condition, the gate induced drain leakage (GIDL) current is determined by the gate and drain voltage (Vgd) and gate bias stress above a certain bias is accompanied by a change in Vth. To understand and model the underlying mechanism of these results, we developed a spatial probability analysis model with mapping of physical quantity (SPAM). The spatial distribution the E-field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and charge trapping (CT) TCAD model. We had to implement different forms of aging model in the two regions: 1) CT in poly-Si/SiOX interface, and 2) DC in the channel bulk (especially, the grain boundary). Finally, our new degradation model allows us to analyze how the GIDL current decreases with various aging conditions and provides a quantitative relationship between the amount of charge trapping and the amount of defect creationI. Fixed negative charge (-) of interface of poly-Si/SiOx(ε(x,y) > εC,f and n(x,y)> nC,f)Qfix (-) (x,y)=αf *[{ε(x,y)-εC,f}/εm,f ]γf_field *[log{n(x,y)/nC,f }]γfn II. Ionized defect density of channel bulk (Grain and GB)(ε(x,y,z) > εC,tA ) NtA (-) =gtA (ε)*exp[-{(EtA-EGA)/WGA}2 ]gtA (ε)= αtA*[{ε(x,y,z)-εC,tA}/εm,tAm ]γtA Figure 1

Ionizing radiation hardness tests of GaN HEMTs for harsh environments

The COTS power transistors based in GaN were exposed to TID effects by 10-keV X-rays. These HEMTs were tested in the On- and Off-state bias conditions. Switching tests were performed before and after irradiation steps. The devices were characterized at temperatures ranging from −50 °C to +75 °C. The results indicate that the GaN-technology is a great candidate to be used in harsh environments, because the tested devices have presented an expressive recovery of its parameters of Vth, gmmax and switching times, after accumulation of 350 krad of TID.

Forward Conduction Instability of Quasi-Vertical GaN p-i-n Diodes on Si Substrates

This article reports trap-related forward conduction instability of GaN quasi-vertical p-i-n diodes grown on a Si substrate. Three hole traps with activation energies of 0.38, 0.60, and 0.70 eV together with one electron trap with an energy level of 0.26 eV under the conduction band were revealed by deep-level transient spectroscopy (DLTS). Pulsed ${I}$ – ${V}$ measurements were performed on a device whose traps were prefilled. The rest time durations and OFF-state bias levels and periods were varied to investigate the forward ${I}$ – ${V}$ recovery phenomenon, which was highly correlated with the carrier detrapping process inside the device. The detrapping process could be greatly accelerated by a reverse bias or a lifted temperature. An “on-the-fly” resistance characterization was carried out to study the time-dependent carrier release process using short positive voltage pulses. The device was further submitted to switch-on transient assessment to investigate the time-resolved dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ evolution. The initial dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio was proportional to the reverse bias level and duration and was gradually decreased after continuous carrier injection until the trapping effects were overwhelmed. With a forward voltage slightly higher than the threshold voltage, it took dozens of milliseconds for the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ to be equal to its static counterpart. It was found that at 350 K, the ON-resistance ratio could reach unit more rapidly than the room temperature case, indicating mitigation of current collapse of p-i-n diodes and their great potential for high-temperature switching applications.

Charge storage impact on input capacitance in p-GaN gate AlGaN/GaN power high-electron-mobility transistors

In this paper, input capacitance (CISS) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. CISS includes gate-to-source capacitance (CGS) and gate-to-drain capacitance (CGD). In comparison with the normally-on HEMTs, it is found that the phenomenon of CISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of CISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of CGS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing CGS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of CGD. Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on CISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the CISS related capacitance design and gate driver optimization of the devices.

Reliability Characterization of Gallium Nitride MIS-HEMT Based Cascode Devices for Power Electronic Applications

We present a detailed study of dynamic switching instability and static reliability of a Gallium Nitride (GaN) Metal-Insulator-Semiconductor High-Electron-Mobility-Transistor (MIS-HEMT) based cascode switch under off-state (negative bias) Gate bias stress (VGS, OFF). We have investigated drain channel current (IDS, Max) collapse/degradation and turn-on and rise-time (tR) delay, on-state resistance (RDS-ON) and maximum transconductance (Gm, max) degradation and threshold voltage (VTH) shift for pulsed and prolonged off-state gate bias stress VGS, OFF. We have found that as stress voltage magnitude and stress duration increases, similarly IDS, Max and RDS-ON degradation, VTH shift and turn-on/rise time (tR) delay, and Gm, max degradation increases. In a pulsed off-state VGS, OFF stress experiment, the device instabilities and degradation with electron trapping effects are studied through two regimes of stress voltages. Under low stress, VTH shift, IDS collapse, RDS-ON degradation has very minimal changes, which is a result of a recoverable surface state trapping effect. For high-stress voltages, there is an increased and permanent VTH shift and high IDS, Max and RDS-ON degradation in pulsed VGS, Stress and increased rise-time and turn-on delay. In addition to this, a positive VTH shift and Gm, max degradation were observed in prolonged stress experiments for selected high-stress voltages, which is consistent with interface state generation. These findings provide a path to understand the failure mechanisms under room temperature and also to accelerate the developments of emerging GaN cascode technologies.

Comparative Study on Dynamic Characteristics of GaN HEMT at 300K and 150K

Dynamic characteristics of GaN HEMT grown on a native substrate were systematically investigated at 300K and 150K. Transfer and output characteristics of the GaN HEMT were measured after various off-state stressing conditions and recovery durations. In addition, a high-speed scheme was employed to finish the measurement within $75~\mu \text{s}$ , and to ensure maximum preservation of stressing/recovery consequences. The threshold voltage instability and current collapse commonly observed at room temperature were mostly diminished at 150K, which was attributed to reduced number of electrons through the metal-semiconductor contact and insufficient number of carriers overcoming the capture potential barrier. Two pulsed I-V measurements, including evaluations with various off-state quiescent bias points and “on-the-fly” on-resistance sampling, confirmed an inefficient electron capture process at 150K, with a time constant larger than dozens of seconds. The output characteristic comparison between hard switch and soft switch at 150K provided direct experimental evidence for electron capture promotion by hot carriers.

Understanding the Threshold Voltage Instability During OFF-State Stress in p-GaN HEMTs

In this letter, we investigate by means of experimental results and TCAD simulations the threshold voltage instability due to OFF-state drain stress in p-GaN gate AlGaN/GaN-on-Si HEMTs. When the drain of the p-GaN HEMT is biased in the OFF-state the threshold voltage (Vth) shows a linear increase up to ~40%. This increase saturates at drain bias voltages above 50 V. The positive Vth shift is attributed to the ionization of acceptor traps in the AlGaN region below the p-GaN gate with the source of these trapping sites suggested to be the p-GaN gate out-diffused Mg dopant atoms. The ionization of the Mg acceptors due to high electric field during OFF-state bias and the removal of the generated holes from the AlGaN region through the gate contact creates the charge conditions for a positive Vth shift. The sharp decrease in the gate drain capacitance (Cgd) for VD <; 50 V, the simulated gate edge electric field reaching its peak for a drain voltage bias VD ~ 50 V and the positive threshold voltage shift observed for negative gate stress further validate the proposed model.

Neutron Irradiation Effects on the Electrical Properties of Previously Electrically Stressed AlInN/GaN HEMTs

This paper analyses the neutron irradiation impact on the electrical performances of unstressed, ON-state, OFF-state, and negative gate bias (NGB) stressed AlInN/GaN HEMTs. These irradiations have resulted in the creation of electron traps that are causing a decrease in the drain current and an increase in the access resistance of the unstressed, ON-state, or OFF-state stressed AlInN/GaN devices. These degradations have been correlated with gamma spectrometry measurements and transmutation reactions occurred during the thermalized neutron irradiation have been highlighted. Despite these phenomena, a rise in drain current and a reduction in access resistance have been observed when NGB stressed AlInN/GaN HEMTs were irradiated with a fluence of $1.2\times 10^{\mathbf {12}}$ neutrons/cm2. The differences between the electrical behaviors of unstressed, ON-state, OFF-state, and NGB stressed devices observed after the neutron bombardment are related to the presence of electron traps in these device structures.

A 6–18-GHz Switchless Reconfigurable Dual-Band Dual-Mode PA MMIC Using Coupled-Line-Based Diplexer

In this paper, a switchless dual-band, dual-mode power amplifier (PA) has been developed for multioctave operation. For the switchless dual-band operation, we proposed a new coupled-line-based diplexer structure. The proposed diplexer operates as a balun at high-band frequencies and the coupled line at low-band frequencies. To better understand the proposed diplexer structure, a detailed analysis is performed based on a coupled-line theory. The interstage and output-stage matching networks of the PA are designed by using the proposed diplexer. To maximize the power-added efficiency (PAE) of the designed PA, turn off the unused band PAs and decide the optimum off-state bias condition of transistors. The designed dual-band, dual-mode PA is fabricated with commercial 0.25- $\mu \text{m}$ GaN HEMT process. The fabricated PA shows over 15-dB small-signal gain at 5–11 GHz in the low-band mode and 9–18 GHz in the high-band mode. The measured average output power and PAE are 35 dBm, 23% in the low-band mode and 37 dBm, 26% in the high-band mode.

Vertical GaN n-channel MISFETs on ammonothermal GaN substrate: Temperature dependent dynamic switching characteristics

Switching of GaN-based vertical-trench gate MISFET on ammonothermal n-type GaN substrate are studied as a function of temperature. Pulsed on-state IV characterization revealed three unexpected independent effects. First, drain current increases with temperature, although electron mobility decreases with temperature. Second, drain current decreases with pulse length, which cannot be explained by heating. Third, dynamic Ron increases with off-state drain bias, which usually is considered as an issue of lateral GaN HFETs only. The drain current temperature dependence is most likely dominated by the low electron mobility in the inversion layer beneath the gate. The field effect channel mobility is estimated as < 10 cm2/V s and can thus be considered as trap limited and thermally activated, Ron decreases from 133 Ω mm at 20 °C to 62 Ω mm at 110 °C. Longer on-state pulses lead to negative charging of the ALD-Al2O3 gate oxide and shift the threshold voltage (DC-Vth ~8 V) positively. With the maximum applicable Vgs = 10 V, the drain current is not saturated yet and Ids thus drops by a factor 2 when increasing the on-state pulse width from 0.2 µs to 20 µs due to the Vth-shift. The observed 10-times dynamic Ron increase with off-state drain bias up to 30 V can be related to possible charging mechanism in the gate oxide as well. Activation energies for different off-state stress voltage are ranged linear between 0.08 eV and 0.26 eV for drain bias stress of Vds = 0 V and 30 V respectively.

Reliability Improvement of GaN Devices on Free-Standing GaN Substrates

In order to analyze the influence of different substrates on the performance of metal–insulator–semiconductor AlGaN/GaN high-electron mobility transistors, devices on free-standing GaN (FS-GaN), silicon, and sapphire substrates with similar AlGaN/GaN top layers were fabricated. Compared with Si and sapphire substrates, the devices on the FS-GaN substrate not only achieve remarkable improvement in the direct current characteristics but also have much better thermal stability and can significantly suppress the self-heating effects, where the current density only decreases by 4% with the channel at 48 °C and an ambient of 25 °C. Owing to the lower trap and dislocation densities in the epitaxial layers, the dynamic performance and reliability of the devices on the FS-GaN substrate are also dramatically improved. With an off-state drain bias of 50 V kept for 10 s, the devices on the FS-GaN substrate only suffer a 10% increase in dynamic on resistance, much lower than the devices on the Si and sapphire substrates. In addition, all the devices were exposed to a 3-MeV proton irradiation with a dose of $\text {3} \times \text {10}^{\text {14}}$ cm−2. Compared with the devices before radiation treatment, the dynamic on resistance increases by 79% with a 20-V off-state stress for the devices on the FS-GaN substrate, while the increase is over 800% for the other devices. The lower performance degradation for the devices on the FS-GaN substrate indicates a lower displacement damage and better irradiation tolerance.

Gate-induced drain leakage current characteristics of p-type polycrystalline silicon thin film transistors aged by off-state stress

Thin film transistors have become crucial components of several electronic display devices. However, high leakage current is a frustrating impediment to increasing the efficiency of these transistors. We have performed an experimental and quantitative study on the effects of off-state bias stress on the characteristics of a p-type polycrystalline silicon (poly-Si) thin film transistor (TFT). The gate-induced drain leakage (GIDL) current under off-state bias stress conditions was investigated by changing gate-source voltage (Vgs) and drain-source voltage (Vds). Off-state bias stress was found to dramatically increase the threshold Vgs from 1 to 11 V, thereby increasing the voltage needed to turn off the TFT, without causing significant changes in on-state current or subthreshold swing. We developed local defect creation and charge trapping models for a technology computer-aided design simulation platform to understand the mechanisms underlying these observed effects. Using the model, we showed that off-state stress induces charge trapping within the local defects of a high electric field region in the TFT channel near the drain. This reduces the electric field and thermionic field-emission current, which in turn lowers the GIDL current by increasing threshold voltage Vgs.