Integrated GaN HEMT Cascode Power Module Stability Analysis under Negative Gate Bias Stress for Power Electronic Applications

Abstract

We present a detailed investigation of two forms of negative gate bias stress in four parallel GaN HEMTs in cascode configuration in this article: (i) pulsed off-state gate bias and (ii) negative bias temperature instability (NBTI). Device statical parameter degradations and instabilities, such as IDS, RDS-ON, GM, max, and IGSS, are evident under low/mid pulsed off-state gate bias stress conditions, according to the measured results of pulsed gate bias stress. Under NBTI experiments, mid/high off-state bias stress with accelerated temperatures, the device demonstrated their excellent stability and negligible degradation of VTH and RDS-ON. These findings pave the way for evaluating device reliability and understanding the failure mechanism caused by negative gate bias stress, allowing emerging GaN cascode technologies to advance faster.