New Degradation Model of LTPs TFT Aged Off-State Bias Stress on Flexible Substrate

Abstract

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented a new degradation model using TCAD simulation. In the off-state bias stress condition, the gate induced drain leakage (GIDL) current is determined by the gate and drain voltage (Vgd) and gate bias stress above a certain bias is accompanied by a change in Vth. To understand and model the underlying mechanism of these results, we developed a spatial probability analysis model with mapping of physical quantity (SPAM). The spatial distribution the E-field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and charge trapping (CT) TCAD model. We had to implement different forms of aging model in the two regions: 1) CT in poly-Si/SiOX interface, and 2) DC in the channel bulk (especially, the grain boundary). Finally, our new degradation model allows us to analyze how the GIDL current decreases with various aging conditions and provides a quantitative relationship between the amount of charge trapping and the amount of defect creationI. Fixed negative charge (-) of interface of poly-Si/SiOx(ε(x,y) > εC,f and n(x,y)> nC,f)Qfix (-) (x,y)=αf *[{ε(x,y)-εC,f}/εm,f ]γf_field *[log{n(x,y)/nC,f }]γfn II. Ionized defect density of channel bulk (Grain and GB)(ε(x,y,z) > εC,tA ) NtA (-) =gtA (ε)*exp[-{(EtA-EGA)/WGA}2 ]gtA (ε)= αtA*[{ε(x,y,z)-εC,tA}/εm,tAm ]γtA Figure 1