Abstract
We conducted experimental and quantitative studies on the effects of off‐state bias stress on the p‐type polycrystalline silicon thin film transistors (TFTs) on flexible substrate and presented an off‐stress bias stress model(=aging model) of leakage current using TCAD simulation. To understand and model the underlying mechanism of these results, we developed a spatial defect generation and charge trapping model utilizing mapping technique. We had to implement different forms of aging model in the two regions: 1) charge trapping in poly‐Si / oxide interface, and 2) defect creation in the channel bulk. Our aging model quantitatively demonstrates why the GIDL current is lowered accompanied by changes in threshold voltage and asymmetric characteristics.
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