Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

Abstract

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.