OFF Current Ratio Research Articles

Effect of copper doping on zinc oxide for potential use in nanowire devices

AbstractZinc oxide is a promising material in semiconductor research owing to its exceptional properties including wide band gap and high carrier mobility. We observe the effect of copper (a promising acceptor species) doping properties of zinc oxide using Density Functional Theory (DFT). Carrier concentration calculations reveal that the copper doping leads to a p-type semiconductor with an increase in hole concentration to the order of 1018 cm−3. The resultant structure is used to build junctionless nanowire transistors. These nanoscale devices exhibit excellent characteristics including a diameter-normalized on-current of more than 500 μA/μm and an on-current to off-current ratio of greater than 5 × 106 for select configurations. In addition, several design parameters are varied, and guidelines are presented that offer improved performance. Graphical abstract Fig. a Copper-doped zinc oxide junctionless transistor (UL represents source/drain underlap) b Cross-sectional view c Drain current vs gate voltage for one of the devices

Impact of bias stress and endurance switching on electrical characteristics of polycrystalline ZnO-TFTs with Al2O3 gate dielectric

Abstract This study experimentally investigates electrical characteristics and degradation phenomena in polycrystalline zinc oxide thin-film transistors (ZnO-TFTs). ZnO-TFTs with Al2O3 gate dielectric, Al-doped ZnO (AZO) source–drain contacts, and AZO gate electrode are fabricated using remote plasma-enhanced atomic layer deposition at a maximum process temperature of 190 °C. We employ positive bias stress (PBS), negative bias stress (NBS), and endurance cycling measurements to evaluate the ZnO-TFT performance and examine carrier dynamics at the channel-dielectric interface and at grain boundaries in the polycrystalline channel. DC transfer measurements yield a threshold voltage of −5.95 V, a field-effect mobility of 53.5 cm2/(V∙s), a subthreshold swing of 136 mV dec−1, and an on-/off-current ratio above 109. PBS and NBS measurements, analysed using stretched-exponential fitting, reveal the dynamics of carrier trapping and de-trapping between the channel layer and the gate insulator. Carrier de-trapping time is 88 s under NBS at −15 V, compared to 1856 s trapping time under PBS at +15 V. Endurance tests across 109 cycles assess switching characteristics and temporal changes in ZnO-TFTs, focusing on threshold voltage and field-effect mobility. The threshold voltage shift observed during endurance cycling is similar to that of NBS due to the contrast in carrier trapping/de-trapping time. A measured mobility hysteresis of 19% between the forward and reverse measurement directions suggests grain boundary effects mediated by the applied gate bias. These findings underscore the electrical resilience of polycrystalline ZnO-TFTs and the aptitude for 3D heterogeneous integration applications.

Enhancing TFET performance through gate length optimization and doping control in phosphorene nanoribbons

In this study, the performance of armchair phosphorene nanoribbons (APNRs) tunnel field-effect transistors (TFETs) is compared to that of conventional Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) based on the self-consistent solution of the Poisson and Schrödinger equation within the non-equilibrium Green's Function formalism and a tight-binding Hamiltonian. As channel length decreases, undesirable consequences such as increased OFF-current and sub-threshold swing can affect MOSFETs' performance. The study thoroughly investigates various aspects of TFET performance, including the impact of channel length, gate length, and doping on parameters like ON-current, OFF-current, the ON-/OFF-current ratio, and sub-threshold swing. An important finding of this research relates to the influence of source and drain doping. We demonstrate that fine-tuning impurity levels directly affects phosphorene nanoribbon TFET (PTFET) performance. The article also investigates the impact of gate length on PTFET performance. New transistor configurations with different gate lengths are proposed in this research. The study shows that optimizing gate length can significantly reduce OFF-current. Furthermore, the combined impact of gate length and doping concentration on PTFET performance is investigated. Through the strategic extension of the gate length towards the drain side and precise adjustments in doping levels, notable improvements in subthreshold swings, ON-current, and the ON-/OFF-current ratio can be realized.

Design and performance analysis of double gate vertically stacked MoS2 nanosheet field effect transistor

In this work we report a vertically stacked nanosheet Field Effect Transistor (NSFET) in double gate configuration using transition metal dichalcogenide (TMD) based molybdenum disulphide (MoS2) as the conducting channel. The performance of the NSFET is analysed for number of channels, different channel thickness, different source/drain contacts. The performance of the device at different temperatures (T) also analysed. The proposed NSFET with three vertically stacked channels, exhibits a ON current (ION) of 30.6 μA μm−1, Subthreshold swing (SS) of 69 mV/dec and ON to OFF current ratio of more than 108 at Vds = 1V. Further the ION can be improved with multi-layer channel thickness. The performance of the vertically stacked MoS2 NSFET in junction less (JL) and inversion mode (IM) is compared, it is concluded from the simulations that JL vertically stacked MoS2 NSFET more immune to short channel effects such as threshold voltage (Vth) roll-off and drain induced barrier lowering (DIBL).

Threshold voltage modulation on a CTL-based monolithically integrated E/D-mode GaN inverters platform with improved voltage transfer performance

This work demonstrates a high-performance monolithically integrated GaN inverters platform, which incorporates enhancement-mode (E-mode) and depletion-mode (D-mode) GaN high-electron-mobility transistors (HEMTs) simultaneously using an Al:HfOx-based charge trapping layer. The developed E-mode HEMT exhibits a positive threshold voltage of 2.6 V, a high ON–OFF current ratio of 1.9 × 108, a current density of 376 mA/mm, and an ON-resistance of 15.31 Ω·mm. Moreover, the direct-coupled field-effect-transistor logic (DCFL) GaN inverter was characterized with and without D-mode device threshold voltage (VTH) modulation, demonstrating improved output swing and switching threshold shift by proposed VTH modulation. The optimized DCFL GaN inverter manifests a switching threshold of 2.34 V, a logic voltage output swing of 4.98 V, and substantial logic-low and logic-high noise margins of 2.16 and 2.49 V, respectively, at a supply voltage of 5 V. These results present a promising approach toward realizing monolithically integrated GaN logic circuits for power IC applications.

Raised Ge-Source with n+ pocket and recessed drain line TFET: A proposal for biosensing applications

In this paper, we present a novel raised Ge-source with an n+ pocket and recessed drain line Tunnel Field-Effect Transistor (TFET). It offers enhanced performance for potential biosensing applications. The proposed device comprises a Ge source with a low bandgap, an n+ pocket, and a larger tunneling area. This results in improved performance characteristics: an ON current of 54.27 μA/μm, an ON-current to OFF-current ratio of 1.5 × 1012, and an average subthreshold swing of 21.3 mV/dec. The recessed drain design eliminates ambipolarity, further enhancing performance. The study thoroughly investigates biosensing capabilities, including DC and transient analyses, evaluating charged and neutral biomolecules (uricase, biotin, 3-aminopropyltriethoxysilane, DNA, keratin, and gelatin). The proposed biosensor, with a higher drain current sensitivity of 1.2 × 109 for gelatin (k = 12) and 3.05 × 108 for keratin (k = 8), outperforms existing approaches, making our proposed biosensor a compelling choice for future low-power biomedical applications.

GaN-based low-power JLDG-MOSFETs: Effects of doping and gate work function

The purpose of this study is to investigate the possibilities of the junction-less double-gate (JLDG) MOSFET structure with gallium nitride (GaN) channel material to overcome the limitations of conventional MOSFET structures in improving device performance at scaled gate lengths and voltages. The design targets of this study are the doping profile (ND), and gate work function (Ф). The device has been modeled using the Silvaco Atlas 2D device simulator. The proposed model has been validated by calibrating it against the parabolic potential-based analytical model for short-channel JLDG MOSFETs in the subthreshold regime of Jazaeri et al. Device figure of merits (FOMs) such as ON-current (ION), ON-OFF current ratio (ION/IOFF), subthreshold swing (SS), and drain-induced barrier lowering (DIBL) have been evaluated. The maximum on-current, (ION) = 0.9 mA/μm, has been achieved by tuning the channel doping concentration (ND) to 1 × 1019 cm−3. Tuning the gate work function, (Ф) also has a substantial effect on the behavior of the device. The lowest OFF-state current (IOFF) of 1.24 × 10−16 A/μm and power dissipation of 9.69 × 10−17 W/μm have been found for gate work-function (Ф) = 5.1 eV (Au). In addition, the on-current to off-current ratio (ION/IOFF) of 7.56 × 1012 revolutionizes the applicability of the device in the semiconductor industry. Thus, the remarkable improvements in device FOMs prove that GaN-based JLDG MOSFETs are a strong contender for applications requiring low-power logic switching in the next generation.

The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs

The aim of this study is to examine the analog/RF performance characteristics of graphene nanoribbon (GNR) field-effect transistors (FETs) using a novel technique called underlap engineering. The study employs self-consistent atomistic simulations and the non-equilibrium Green's function (NEGF) formalism. Initially, the optimal underlap length for the GNR-FET by device has been determined evaluating the ON-current (ION) to OFF-current (IOFF) ratio, which is a critical parameter for digital applications. Subsequently, the impact of underlap engineering on analog/RF performance metrics has been analyzed and conducting a comprehensive trade-off analysis considering parameters such as intrinsic-gain, transistor efficiency, and device cut-off frequency. The results demonstrate that the device incorporating the underlap mechanism exhibits superior performance in terms of the ION/IOFF ratio, transconductance generation factor (TGF), output resistance (r0), intrinsic gain (gmr0), gain frequency product (GFP), and gain transfer frequency product (GTFP). However, the device without the underlap effect demonstrates the highest transconductance (gm) and cut-off frequency (fT). Finally, a linearity analysis has been conducted to compare the optimized GNR-FET device with the conventional GNR-FET device without the underlap effect.

Solution-processed zirconium acetylacetonate charge-trap layer for multi-bit nonvolatile thin-film memory transistors

ABSTRACT The charge trap property of solution-processed zirconium acetylacetonate (ZAA) for solution-processed nonvolatile charge-trap memory (CTM) transistors is demonstrated. Increasing the annealing temperature of the ZAA from room temperature (RT) to 300°C in ambient, the carbon double bonds within the ZAA decreases. The RT-dried ZAA for the p-type organic-based CTM shows the widest threshold voltage shift (∆VTH ≈ 80 V), four distinct V THs for a multi-bit memory operation and retained memory currents for 103 s with high memory on- and off-current ratio (IM,ON/IM,OFF ≈ 5Ⅹ104). The n-type oxide-based CTM (Ox-CTM) also shows a ∆V TH of 14 V and retained memory currents for 103 s with I M,ON/I M,OFF ≈ 104. The inability of the Ox-CTM to be electrically erasable is well explained with simulated electrical potential contour maps. It is deduced that, irrespective of the varied solution-processed semiconductor used, the RT-dried organic ZAA as CTL shows the best memory functionality in the fabricated CTMs. This implies that the high carbon double bonds in the low-temperature processed ZAA CTL are very useful for low-cost multi-bit CTMs in flexible electronics.

Aqueous electrolyte-gated solution-processed metal oxide transistors for direct cellular interfaces.

Biocompatible field-effect-transistor-based biosensors have drawn attention for the development of next-generation human-friendly electronics. High-performance electronic devices must achieve low-voltage operation, long-term operational stability, and biocompatibility. Herein, we propose an electrolyte-gated thin-film transistor made of large-area solution-processed indium-gallium-zinc oxide (IGZO) semiconductors capable of directly interacting with live cells at physiological conditions. The fabricated transistors exhibit good electrical performance operating under sub-0.5 V conditions with high on-/off-current ratios (>107) and transconductance (>1.0 mS) over an extended operational lifetime. Furthermore, we verified the biocompatibility of the IGZO surface to various types of mammalian cells in terms of cell viability, proliferation, morphology, and drug responsiveness. Finally, the prolonged stable operation of electrolyte-gated transistor devices directly integrated with live cells provides the proof-of-concept for solution-processed metal oxide material-based direct cellular interfaces.

High-Performance P- and N-Type SiGe/Si Strained Super-Lattice FinFET and CMOS Inverter: Comparison of Si and SiGe FinFET.

This research presents the optimization and proposal of P- and N-type 3-stacked Si0.8Ge0.2/Si strained super-lattice FinFETs (SL FinFET) using Low-Pressure Chemical Vapor Deposition (LPCVD) epitaxy. Three device structures, Si FinFET, Si0.8Ge0.2 FinFET, and Si0.8Ge0.2/Si SL FinFET, were comprehensively compared with HfO2 = 4 nm/TiN = 80 nm. The strained effect was analyzed using Raman spectrum and X-ray diffraction reciprocal space mapping (RSM). The results show that Si0.8Ge0.2/Si SL FinFET exhibited the lowest average subthreshold slope (SSavg) of 88 mV/dec, the highest maximum transconductance (Gm, max) of 375.2 μS/μm, and the highest ON-OFF current ratio (ION/IOFF), approximately 106 at VOV = 0.5 V due to the strained effect. Furthermore, with the super-lattice FinFETs as complementary metal-oxide-semiconductor (CMOS) inverters, a maximum gain of 91 v/v was achieved by varying the supply voltage from 0.6 V to 1.2 V. The simulation of a Si0.8Ge0.2/Si super-lattice FinFET with the state of the art was also investigated. The proposed Si0.8Ge0.2/Si strained SL FinFET is fully compatible with the CMOS technology platform, showing promising flexibility for extending CMOS scaling.

Multilevel Fully Logic-Compatible Latch Array for Computing-in-Memory

In this study, a multilevel logic-compatible two-transistor-two-resistor (2T2R) latch array for computing-in-memory (CIM) is proposed, featuring high power efficiency, fast response, and high resolution. Combining the resistive switching pairs of the Hf-based gate dielectric layers and a near-threshold-operated output transistor for resistance ratio enhancement, non-volatile memory (NVM) latch arrays are implemented on Si. Taking the advantage of the stable and reliable output by complementary resistive states, the ON– OFF current ratio can be greatly improved. In addition, low power consumption by the near-threshold operation, high data density by multilevel cell, and the novel latch arrays successfully enhance the accuracy and lower power of the analog multiply–accumulate-operation (MAC) and become a promising module in the CIM applications.

Ferroelectric-gated variable-area capacitors with large capacitance tuning ratio using Ce-doped HfO2 film for both gate insulator and capacitor layer

We demonstrate a three-terminal variable-area capacitor integrated with a ferroelectric-gate field-effect transistor (FeFET) and a ferroelectric capacitor. A FeFET using an indium tin oxide (ITO) channel and a ferroelectric Hf0.86Ce0.14O2 gate insulator was fabricated by chemical solution deposition. The fabricated FeFET exhibited a high on-current of ∼0.18 mA μm−1 and a large on-/off-current ratio of 106. The large charge controllability of the FeFET allows the conductive ITO channel to act as an electrode switch that connects and disconnects two capacitors. In order to increase the capacitance density and the capacitance tuning ratio (CTR), we propose a structure wherein a 25-nm-thick ferroelectric film is applied as both a gate insulator and a capacitor. The proposed structure exhibited a large capacitance density of 12.5 nF mm−2 and a wide CTR of approximately 10 000. This work facilitates future integration of passive and active components for advanced highly efficient and miniaturized electronics.

Study of ambipolar and linearity behavior of the misaligned double gate-drain dopant-free Nano-TFET: Design and performance enhancement

Work done in this article demonstrates the charge plasma based misaligned double gate-drain doping less tunnel field effect transistor. Designed devices such as perfectly aligned and misaligned, both are optimized by considering the secondary drain in order to investigate ambipolar and linearity behavior. As the work function of secondary drain increases reduction in the ambipolar current is observed with a little degradation in ON state current. It presents a tradeoff between ambipolar current and ON current hence suitable work function of secondary drain is necessary for the proper working of the device. Analog parameters such as ON current, ambipolar current, subthreshold slope, ON to OFF current ratio, ON current to ambipolar current ratio, threshold voltage are analyzed with respect to secondary drain. In order to investigate the device performance for low voltage and low noise applications various linearity parameters such as higher order transconductances, higher order harmonic distortions, higher order intermodulation point and transconductance gain factor have also been demonstrated all the designed structures. The values of ON current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 52 μA, 30 μA, 18 μA and 12 μA respectively. And ambipolar current for perfectly aligned, underlap, overlap and both gate misaligned structure at 4.2eV of secondary drain work function is 3 pA, 23 pA, 247 pA and 705 pA respectively.

Proposal and performance evaluation of delta doped negative capacitance tunneling field transistor: A simulation study

Here we proposes and optimizes a delta doped dual spacer negative capacitance TFET to improve ON current, steeper sub threshold slope, and ON to OFF current ratio. The inclusion of the delta layer and high K spacer on the source side improves the characteristics by increasing the electric field and lowering the surface potential at the source channel interface. The incorporation of the FE layer in the gate stack creates the negative capacitance effect and improves the performances due to voltage amplification process. Here, FE-HFO2 is taken as a ferroelectric material. A very high current ratio of the order 1.8 × 1012 with a substantially low average sub threshold swing of 18 mV/decade is achieved which make it suitable for low power applications. Finally, for optimized NCFETs, the influence of temperature (200 K–350 K) is examined at tfe = 5 nm for switching characteristics.

Charge-plasma based symmetrical-gate complementary electron–hole bilayer TFET with improved performance for sub-0.5 V operation

In this paper, the complementary charge-plasma (CP) based symmetrical-gate electron–hole bilayer (EHB) tunnel field-effect transistor (TFET) at a low operating voltage (⩽0.5 V) is introduced. Where, by using CP technique, the source/drain and EHB-channel is induced by depositing metal electrode with appropriate work function. Moreover, the immunity against random dopant fluctuations and the feasibility of a self-aligned process due to a symmetrical top/bottom gate arrangement without the need for a high thermal annealing process make the fabrication of the proposed EHB-TFET very reliable and efficient. Moreover, by implementing the density gradient quantum correction model, the quantum confinement and its effect on confining the 2D electron–hole concentration are also corrected as the proposed device has a smaller channel thickness of 5 nm. The proposed device shows superior performance against almost all Si-based CP-TFETs with a higher ON-current of 47.33 μA μm−1, a smaller average subthreshold swing of 13.53 mV dec−1 and a high ON-current to OFF-current ratio of 2.16 × 1013. This indicates that the proposed device is a promising candidate for future low-power applications.

Enhanced Electrical and Mechanical Performance of InSnZnO TFTs With Multifunctional Laminated Organic Passivation Layer

To realize high-performance and stable electrical characteristics for ZnO-based thin-film transistors (TFTs) under various environments, we propose InSnZnO (ITZO) TFTs with multifunctional laminated organic (MLO) passivation layers (PVLs). The MLO PVLs were constructed from self-assembled monolayers (SAMs) and an ultraviolet (UV) light absorber-modified polydimethylsiloxane (PDMS) layer. The SAMs can passivate the ITZO surface and suppress the chemical reaction during the spin-coating process, and the modified PDMS layer can block UV light. The MLO-treated ITZO TFTs exhibited a high-performance and robust stability with high mobility (~21.18 cm2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> V−1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot $ </tex-math></inline-formula> s−1), a considerable ON– OFF current ratio (~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.65\times10$ </tex-math></inline-formula> 9), and a steep subthreshold slope (~100 mV/dec). The shift of the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\textit V}_{{\mathrm {th}}}$ </tex-math></inline-formula> ) under gate bias stress and UV light illumination stress was investigated for the devices with different PVLs. The ITZO TFTs with MLO PVLs showed improved stability under positive gate bias stress (PBS), positive gate bias illumination stress (PBIS), and negative gate bias illumination stress (NBIS) compared to untreated and SAM-treated ITZO TFTs. Furthermore, the MLO-treated ITZO TFTs achieved a weak response to 365-nm UV light and showed superb stability with the negligible change of electrical performance, even after a 1-h water soaking test and a 100-day storing test. In addition, the MLO PVL exhibited high flexibility without signs of cracking even after 10 000 bending cycles and was proven suitable for fabricating flexible oxide TFTs.

Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM.

As the physical dimensions of cell transistors in dynamic random-access memory (DRAM) have been aggressively scaled down, buried-channel-array transistors (BCATs) have been adopted in industry to suppress short channel effects and to achieve a better performance. In very aggressively scaled-down BCATs, the impact of structural variations on the electrical characteristics can be more significant than expected. Using a technology computer-aided design (TCAD) tool, the structural variations in BCAT (e.g., the aspect ratio of the BCAT recess-to-gate length, BCAT depth, junction depth, fin width, and fin fillet radius) were simulated to enable a quantitative understanding of its impact on the device characteristics, such as the input/output characteristics, threshold voltage, subthreshold swing, on-/off-current ratio, and drain-induced barrier lowering. This work paves the road for the design of a variation-robust BCAT.

Mixed tin-lead perovskite nanorod-based resistive memory device

• Perovskite nanorods synthesis by intercalation of long-chain organic cations. • Use of oleylammonium organic cation into bulk methylammonium tin-lead bromides as cations. • Poly(methyl methacrylate) encapsulated nanorods are excellent memristor active layer. SET voltage lowered to ∼ 0.5 V and ON OFF current ratios enhanced to ∼10 5 . Stable mixed cation (tin-lead) perovskite nanorods results from intercalating long-chain organic ligand- oleylamine into perovskite 3D (CH 3 NH 3 PbBr 3 ) structure using the ligand-assisted re-precipitation method. A spin-coated nanorod film works as an active layer for resistive memory devices by sandwiching nanorod film between two electrodes with a switching voltage of 1.4 V. A poly(methyl methacrylate) passivated nanorod film results in better resistive memory properties by exploiting advantages of both insulating poly(methyl methacrylate) and semiconducting perovskite nanorods. The passivation enhances the stability of the device, protecting electrodes from reacting with the perovskite layer. The structure lowers the current in the high resistance state, increasing the ON OFF current ratio to ∼ 10 5 . The device exhibits non-volatile rewritable resistive switching characteristics with a switching voltage ∼ 0.5 V. The conduction mechanism involved in the switching action is explained from the relation between current-voltage as space charge limited conduction.

Low temperature (

This study first attempted to fabricate and study the properties of flash memory devices using amorphous In-Ga-sn-O (IGTO) material as a channel material. Compared with devices using amorphous In-Ga-Zn-O (IGZO) material as a channel material, amorphous IGTO flash memory devi ces exhibit improved memory characteristics with faster write/erase speeds (10 µs), improved program/erase (P/E) efficiency, lower sub-threshold swing (SS), higher field effect mobility (µFE) and enhanced on-current to off-current ratio (ION/IOFF). The erasing method and possible mechanism to enhance erasing efficiency utilizing light-assisted negative gate biasing were discussed in this paper. The photo transition is closely related to oxygen vacancy, therefore, the light-assisted approach photo-ionizing oxygen vacancies to generate holes could be a way to achieve erasing under the negative gate bias. Compared with amorphous IGZO thin film, amorphous IGTO thin film has a lower electron affinity and more oxygen vacancies that can provide more holes. In the P/E characterization under different circumstances, amorphous IGTO devices had a wider memory window (MW), and longer retention behaviors. These properties broaden the applications of modern flash device circuits and serve as a reference for future advances in flash storage technology.