Number Of Gate Fingers Research Articles

Direct parameter-extraction method for MOSFET noise model from microwave noise figure measurement

A new method for the determination of the four noise parameters of the metal oxide semiconductor field effect transistors (MOSFETs) based on the noise figure measurement system without microwave tuner is presented. The noise parameters are determined based on a set of analytical expressions of noise parameters by fitting the measured noise figure of the active device. These expressions are derived from an accurate small signal and noise equivalent circuit model, which takes into account the substrate parasitics, pad capacitances, and series inductances. On-wafer experimental verification is presented and a comparison with tuner based method is given. Good agreement is obtained between simulated and measured results for 0.5 × 5 × 16 μm, 0.35 × 5 × 16 μm and 0.18 × 5 × 16 μm (gate length × number of gate fingers × unit gate width) MOSFETs.

Design and model studies for solid-state power amplification at 210 GHz

The high millimeter-wave (mmW) frequency range offers new possibilities for high-resolution imaging and sensing as well as for high data rate wireless communication systems. The use of power amplifiers of such systems boosts the performance in terms of operating range and/or data rate. To date, however, the design of solid-state power amplifiers at frequencies about 210 GHz suffers from limited transistor model accuracy, resulting in significant deviation of simulation and measurement. This causes cost and time consuming re-design iterations, and it obstructs the possibility of design optimization ultimately leading to moderate results. For verification of the small-signal behavior of our in-house large-signal transistor model, S-parameter measurements were taken from DC to 220 GHz on pre-matched transistors. The large-signal behavior of the transistor models was verified by power measurements at 210 GHz. After model modification, based on process control monitor (PCM) measurement data, the large-signal model was found to match the measurements well. A transistor model was designed containing the statistical information of the PCM data. This allows for non-linear spread analysis and reliable load-pull simulations for obtaining the highest available circuit performance. An experimental determination of the most suitable transistor geometry (i.e. number of gate fingers and gate width) and transistor bias was taken on 100 nm gate length metamorphic high electron mobility transistor (mHEMT) transistors. The most suitable combination of number of fingers, gate width and bias for obtaining maximum gain, maximum output power, and maximum power added efficiency (PAE) at a given frequency was determined.

Finite-element simulations of the effect of device design on channel temperature for AlGaN/GaN high electron mobility transistors

The effect of device design on maximum channel temperature for AlGaN/GaN high electron mobility transistors was investigated through finite element thermal simulations for dissipated power densities up to 5 W mm−1. The effects of substrate material, die size, and number of gate fingers were examined, as well as the divergence between maximum channel temperatures for two dimensional and three dimensional simulations. The maximum temperature increased as the die size decreased beyond a critical distance from the gates. The critical distance was dependent on the substrate material, with SiC requiring the smallest critical distance. At the maximum dissipated power, the temperature increased above ambient more than 300 °C for devices on sapphire substrates compared to an increase of 44 °C for devices on SiC substrates. As the number of gate fingers increased, the maximum channel temperature also increased, and a temperature gradient was observed along the gate width as well as between gate fingers.

RF CMOS modeling: a scalable model of RF-MOSFET with different numbers of fingers

A novel scalable model for multi-finger RF MOSFETs modeling is presented. All the parasitic components, including gate resistance, substrate resistance and wiring capacitance, are directly determined from the layout. This model is further verified using a standard 0.13 μm RF CMOS process with nMOSFETs of different numbers of gate fingers, with the per gate width fixed at 2.5 μm and the gate length at 0.13 μm. Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.

The Enhanced Role of Shallow-Trench Isolation in Ionizing Radiation Damage of 65 nm RF-CMOS on SOI

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

Impact of Proton Irradiation on the RF Performance of 65 nm SOI CMOS Technology

The effects of 63 MeV proton irradiation on 65 nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. High-frequency measurements show that the input and output matching conditions are not affected, up to a cumulative dose of 4.1 Mrad. The implications of proton irradiation on device design constraints, particularly device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that multi-finger CMOS devices with higher finger width are better-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

Effects of Multigate-Feeding Structure on the Gate Resistance and RF Characteristics of 0.1-$\mu{\hbox{m}}$ Metamorphic High Electron-Mobility Transistors

We investigate the effects of a multigate-feeding structure on the gate resistance (Rg) and RF characteristics of the high electron-mobility transistors (HEMTs). In this structure, the increase of Rg with the gatewidth (W) is minimized; therefore, high maximum frequency of oscillation (fmax) is achieved. Various numbers of gate feedings (Ngf) using the air-bridge interconnections are adopted for fabricating the 0.1-mum depletion-mode metamorphic HEMTs. From these structures, we observe great reduction in Rg with the increase of Ngf, and their relationship is given by Rgprop 1/[2middot(Ngf-1)]2, where Ngf=2,3,4,...; on the other hand, the effects of Ngf on other small-signal parameters are negligible. Calculated cutoff frequency (fT) and fmax from the extracted small-signal parameters all show good agreement with the measurement results. fT is slightly decreased with the increase of Ngf due to the increase of gate-to-source capacitance. fmax is, however, greatly increased with Ngf, and this effect becomes greater at longer total gatewidth (W times number of gate fingers) . This is due to the smaller Rg at greater Ngf in the multigate-feeding structure. We propose that this gate-feeding structure provides a very effective way to suppress Rg and maximize fmax for the applications of the HEMTs with long W.

Microwave noise modeling for PHEMT using artificial neural network technique

An improved noise model for pseudomorphic high electron mobility transistors (PHEMT) based on the combination of the artificial neural network (ANN) and conventional equivalent circuit modeling technique is presented. The frequency dispersion of the gate noise model parameter P, drain noise model parameter R, and the correlation coefficient C have been taken into account by using an ANN model. The influence of the gate leakage current can be accommodated by using the proposed noise model. The noise model parameters are determined directly from on wafer noise parameters measurement based on the noise correlation matrix technique. Good prediction for noise parameters and significant improvements of the accuracy of noise parameters are obtained up to 26 GHz for 2 × 40 μm gate width (number of gate fingers × unit gate width) 0.25 μm Double Heterojunction δ-doped PHEMTs over a wide range of bias points. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.

Thermal Modeling of Graphene Layer on the Peak Channel Temperature of AlGaN∕GaN High Electron Mobility Transistors

We report that the deposition of graphene as a heat spreading layer on /sapphire high electron mobility transistors (HEMT) can lower the temperature of localized hot spots, which can reach as high as . As the number of gate fingers increased, the peak channel temperature also increased. From our simulation, graphene was shown to be extremely effective in distributing the localized heat in both SiC and sapphire substrates. The reliability of HEMT can be remarkably improved by using a graphene layer because it can act as a heat-spreading layer and lower the temperature of localized hot spots, which are known to limit device performance and activate the formation of defects.

Radio Frequency Characteristics of Multifinger 0.1 µm Metamorphic High-Electron-Mobility Transistors Depending on Number of Gate Fingers and Gate Width

We investigate the effects of the number of gate fingers (N) and gate width (W) on the high-frequency characteristics of 0.1 µm depletion-mode metamorphic high-electron-mobility transistors (MHEMTs). The extracted gate-to-source capacitance (Cgs), gate-to-drain capacitance (Cgd), intrinsic transconductance (gm,int), and drain conductance (Gds) are proportional to total gate width (wt), whereas intrinsic resistance (Ri) and source resistance (Rs) are inversely proportional to wt. Gate resistance (Rg) linearly increases at various slopes with non-zero gate resistances at zero gate width depending on N. The cutoff frequency ( fT) and maximum frequency of oscillation ( fmax) are calculated using a small-signal model and curve-fitting equations extracted from each small-signal parameter. fT is almost constant; however, fmax is a strong function of Rg1/2 and is affected by both N and wt. A large wt produces a low fmax; however, at a given wt, increasing the number of gate fingers is more efficient than increasing single gate width for maximizing the fmax.

Direct Measurement of Low Noise 90-nm-Node RF Metal Oxide Semiconductor Field-Effect Transistors Using New Layout

Using a new layout, the microstrip line layout, to screen the RF noise generated by a lossy substrate, a noise figure (NFmin) of 0.46 dB at 10 GHz has been directly measured for 8-gate-finger 90-nm-node MOSFETs (LG=65 nm). This was achieved without the need for de-embedding. The low NFmin in metal oxide semiconductor field-effect transistors (MOSFETs) with a small number of gate fingers can also reduce DC power consumption. The data was found to be consistent with a simulation of the DC current–voltage (I–V), S-parameter, and NFmin characteristics.

Relationships between common source, common gate, and common drain FETs

This paper comprehensively analyzes the relationship between common source (CS), common gate (CG), and common drain (CD) field-effect transistors (FETs). The signal and noise parameters of the CG and CD configuration can be obtained directly by using a simple set of formulas from CS signal and noise parameters. All the relationships provide a bi-directional bridge for the transformation between CS, CG, and CD FETs. This technique is based on the combination of an equivalent-circuit model and conventional two-port network signal/noise correlation matrix technique. The derived relationships have universal validity, but they have been verified at 2/spl times/40 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) double-heterojunction /spl delta/-doped AlGaAs/InGaAs/GaAs pseudomorphic high electron-mobility transistor with 0.25-/spl mu/m gate length. Good agreement has been obtained between calculated and measured results.

An Approach for Determining PHEMT Small-Signal Circuit Model Parameters Up to 110GHz

This paper describes a method to determine the small-signal equivalent circuit model elements for Double Heterojunction δ-doped PHEMTs, which combines the analytical approach and empirical optimization procedure. The PAD capacitances are determined by measuring an open structure which consists of only the pads. Intrinsic elements determined by a conventional analytical parameter transformation technique are described as function of extrinsic elements. Variation ranges of extrinsic elements for optimization are obtained by using coldfet method. An excellent fit between measured and simulated S-parameters in the frequency range of 2-110GHz is obtained for 2×100um gate width (number of gate fingers × unit gate width) DH PHEMT.

A new method for determination of parasitic capacitances for PHEMTs

A new direct extraction method for the determination of the parasitic capacitances of PHEMTs is presented in this paper. This method is based on a general scalable small signal equivalent circuit model under pinch-off bias condition. The main advantage of this approach is that all parasitic capacitances including Cpg, Cpd and Cpgd can be extracted simultaneously by using PHEMTs of different sizes but with the same pad structure. Good agreement is obtained between modelled and measured results for 2 × 20 µm, 2 × 40 µm, 2 × 60 µm and 2 × 100 µm gate width (number of gate fingers × unit gate width) double heterojunction δ-doped PHEMTs.

A new method for pHEMT noise-parameter determination based on 50-/spl Omega/ noise measurement system

A new method for determining the four noise parameters of pseudomorphic high electron-mobility transistors (pHEMTs) based on a 50-/spl Omega/ noise measurement system without a microwave tuner is presented. The noise parameters are determined based on the noise correlation matrix technique by fitting the measured noise figure of the active device. On-wafer experimental verification up to 26 GHz is presented and a comparison with a tuner-based method is given. The scaling rules for noise parameters have also been determined. Good agreement is obtained between simulated and measured results for 2/spl times/20 /spl mu/m, 2/spl times/40 /spl mu/m, and 2/spl times/60 /spl mu/m gatewidth (number of gate fingers /spl times/ unit gatewidth) 0.25-/spl mu/m double-heterojunction /spl delta/-doped pHEMTs.

RF noise in 0.18-μm and 0.13-μm MOSFETs

Studied the gate finger number and gate length dependence on minimum noise figure (NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> ) in deep submicrometer MOSFETs. A lowest NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> of 0.93 dB is measured in 0.18-μm MOSFET at 5.8 GHz as increasing finger number to 50 fingers, but increases abnormally when above 50. The scaling gate length to 0.13 μm shows larger NFmin than the 0.18-μm case at the same finger number. From the analysis of a well-calibrated device model, the abnormal finger number dependence is due to the combined effect of reducing gate resistance and increasing substrate loss as increasing finger number. The scaling to 0.13-μm MOSFET gives higher NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> due to the higher gate resistance and a modified T-gate structure proposed to optimize the NF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> for further scaling down of the MOSFET.

Millimeter-wave FET modeling using on-wafer measurements and EM simulation

Electron device modeling is a challenging task at millimeter-wave frequencies. In particular, conventional approaches based on lumped equivalent circuits become inappropriate to describe complex distributed and coupling effects, which may strongly affect the transistor performance. In this paper, an empirical distributed FET model is adopted that can be identified on the basis of conventional S-parameter measurements and electromagnetic simulations of the device layout. The consistency of the proposed approach is confirmed by robust scaling properties, which enable millimeter-wave small-signal S-parameters to be predicted as a function of the device periphery and number of gate fingers. Moreover, it is shown how the model identified on the basis of standard S-parameter measurements up to 50 GHz can be efficiently exploited in order to obtain reasonably accurate small-signal prediction up to 110 GHz. Extensive experimental validation is presented for 0.2-/spl mu/m pseudomorphic high electron-mobility transistors devices.

Optimization of Heterojunction Devices for High-Frequency and Low-Noise Operation

One of the main objectives of modern Microelectronics is the fabrication of devices with increasing cutoff frequency and decreasing level of noise. At this moment, the best devices for high-frequency low-noise behavior are AlInAs/GaInAs HEMTs (InP based). In this work a complete analysis of ultra-short-gate AlInAs/GaInAs HEMTs has been performed by using a semiclassical Monte Carlo simulation. The validity of the model has been checked through the comparison of the simulated results with static, dynamic and noise experimental measurements of real 100-nm-gate HEMTs. In order to reproduce the experimental results, we have included in the model some important real effects such as degeneracy, surface charges, T-shape of the gate, presence of dielectrics and contact parasitics. We have then studied the influence of the parasitic resistances width of the devices, the number of gate fingers, the reduction of the gate down to 50 nm, together with the effect of the value of the 8-doping and the recess length With the use of computer simulations we will be able to obtain some design rules avoiding the expensive `test and error' procedure.

Electrothermal modelling of GaAs MESFETs

In this paper a new analytic electrothermal model of a GaAs FET is proposed in order to evaluate the thermal field in the semiconductor body for an easy, fast and reliable layout design using a personal computer. The contribution to the thermal resistance of all the top and bottom layers of a typical chip and the interaction of the channel temperature with the drain current are taken into account. A comparison with a three-dimensional finite-difference simulator and experimental data confirms the accuracy of the model. The CAD tool in which the mathematical model has been implemented can be used for the layout design since it is able to calculate the optimal spacing between contiguous devices to minimize the mutual thermal coupling and also the optimal number of gate fingers and gate-to-gate spacing of a single power device with a multigate layout. The proposed technique is general and can be applied to silicon as well as to heterojunction FET devices.

Monte Carlo simulator for the design optimization of low-noise HEMTs

A complete analysis of low-noise 0.1 /spl mu/m gate AlInAs-GaInAs HEMT's has been performed by using a semiclassical Monte Carlo simulation. The validity of the model has been checked through the comparison of the simulated results with static, dynamic and noise experimental measurements of real HEMTs. In order to reproduce the experimental results, we have included in the model some important real effects such as degeneracy, surface charges, T-shape of the gate, presence of dielectrics and contact resistances. Moreover, the extrinsic parameters of the devices have been added to the usual intrinsic small-signal equivalent circuit, thus allowing the calculation of the real noise of the HEMTs (characterized using the extrinsic minimum noise figure). In this way, we make possible not only the comparison with the experimental noise results, but also the analysis of the influence of the parasitic elements, the device width or the number of gate fingers on the noise of the HEMTs. The reliability of the simulator allows us to realize "computer experiments" which will make faster and cheaper the optimization process of the device design.