Abstract
In this paper a new analytic electrothermal model of a GaAs FET is proposed in order to evaluate the thermal field in the semiconductor body for an easy, fast and reliable layout design using a personal computer. The contribution to the thermal resistance of all the top and bottom layers of a typical chip and the interaction of the channel temperature with the drain current are taken into account. A comparison with a three-dimensional finite-difference simulator and experimental data confirms the accuracy of the model. The CAD tool in which the mathematical model has been implemented can be used for the layout design since it is able to calculate the optimal spacing between contiguous devices to minimize the mutual thermal coupling and also the optimal number of gate fingers and gate-to-gate spacing of a single power device with a multigate layout. The proposed technique is general and can be applied to silicon as well as to heterojunction FET devices.
Published Version
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