Asynchronous Circuits Research Articles

Efficient multi-objective optimization through parallel surrogate-assisted local search with tabu mechanism and asynchronous option

Multi-objective optimization is challenging for computationally expensive objectives because most optimization methods rely on a large number of function evaluations to approach the Pareto-optimal front. To this end, this article develops a novel multi-objective optimization algorithm, the Multi-Objective Parallel Local Surrogate-assisted search (MOPLS) algorithm, which combines surrogate approximation and parallel computing. In each iteration, MOPLS incorporates a tabu mechanism to determine new points for expensive evaluations via a series of independent surrogate-assisted local searches. A master–worker architecture in MOPLS allows the algorithm to conduct either synchronous or asynchronous parallel processing. On a number of benchmark problems, MOPLS outperforms recent surrogate-assisted algorithms within a limited computational budget. Empirical results from parallel experiments indicate that MOPLS can significantly improve its efficiency through parallelism, and the asynchronous MOPLS shows advantages in handling objectives with non-constant evaluation times. Finally, the better performance of MOPLS over alternatives in calibrating a complex watershed simulation model demonstrates its competitiveness in solving real-world engineering applications.

Distributed approximate minimal Steiner trees with millions of seed vertices on billion-edge graphs

In this paper, we present a parallel 2-approximation Steiner minimal tree algorithm and its MPI-based distributed implementation. In place of expensive distance computations between all pairs of seed vertices, the solution we employ exploits a cheaper Voronoi cell computation. Our design leverages asynchronous processing and message prioritization to accelerate convergence of distance computations, and harnesses vertex and edge centric processing to offer fast time-to-solution. We demonstrate scalability and performance using real-world graphs with up to 128 billion edges and 512 compute nodes, and show the ability to find Steiner trees with up to one million seed vertices. Using 12 data instances, we present comparison with the state-of-the-art exact solver, SCIP-Jack, and two sequential 2-approximate algorithms. We empirically show that, on average, the total distance of the Steiner tree identified by our solution is 1.1290 times greater than the Steiner minimal tree – well within the theoretical approximation bound of 2.

Signal Transition Graphs for Asynchronous Data Path Circuits

The paper proposes a method for constructing signal transition graphs (STGs), which are directly mapped into asynchronous circuits for data processing. The advantage of the proposed method is that the resulting circuits are not only output-persistent, but also conformant to the environment. In other approaches, the environment is specified implicitly and/or inexactly and therefore they guarantee only output persistence. The conformation can be verified if both the circuit and its environment are specified by STGs. As an example, we consider a module realizing the function AND2. This module can either wait for both 1s or evaluate the function as soon as at least one 0 arrives. For each case, we draw up a separate STG (scenario) and map it into NCL gates. To provide such a mapping, we specify the behaviors of NCL gates by STG protocols. For data path, such an STG always contains alternative branches with the so-called garbage transitions at the gate inputs. The garbage transitions on a certain wire mean that the circuit is sensitive to the delay in this wire. Ignoring the garbage may lead to a violation of conformation or/and output persistence. For example, in the combinational part of the NCL circuits, the garbage appears on the inputs of NCL gates, and therefore these circuits are not delay insensitive.

РОЗРОБКА ІНТЕЛЕКТУАЛЬНОЇ СИСТЕМИ НАВІГАЦІЇ ТА ПРОСТОРОВОЇ ОРІЄНТАЦІЇ ДЛЯ ЛЮДЕЙ З ВАДАМИ ЗОРУ

A prototype of an information and communication navigation and spatial orientation system for people with visual impairments has been developed based on a mobile device. The prototype has several advantages, including portability, convenience, and ease of use. This is achieved through a harmonious combination of optimized software modules that provide data collection, navigation, intelligent analytics, and image processing within a single smartphone. To implement the prototype, stages of development of the information and communication system were previously conducted, subject area analysis was carried out, software and hardware options were researched, and an architecture was designed based on an algorithm for asynchronous processing of a large stream of data. The result of the work is a verified basic prototype of the system, ready for use in testing conditions and data collection for further research.

Components to Support Choice in Self-Timed Asynchronous Design Flows

The design of digital circuits on recent technologies brings several challenges, among which robustness to variations stands out. Variation sources are multiple, and the evolution of integrated circuit fabrication techniques increases the number and relevance of such sources, and the complexity of ensuring circuit robustness against them. Some design paradigms naturally counter variations of one or more types. Asynchronous self-timed design is one such paradigm that can provide robustness to process, voltage, temperature, ageing and IR drop variations, to cite some of the main types. This paper proposes an enhancement to the Pulsar environment, a recently proposed open source automated flow for the design of self-timed clockless circuits.The six components proposed here enable describing choices and decisions on the flow of data tokens inside asynchronous circuits.Design capture in Pulsar can then employ these. To implement the abstract (synthesis-enabled) components, the paper also bringsthe proposal of the handshaking mutex, a versatile complex gate that eases the design of probe and arbiter, the two most complex among the new components. Results demonstrate the new version of Pulsar is more powerful than the previous, baseline, version, enabling the design capture and the automated synthesis steps of more complex asynchronous self-timed circuits. They also indicate the handshaking mutex operates correctly, and with a good level of attested fairness.

A queueing model of visual search

Understanding how attentional resources are deployed in visual processing is a fundamental and highly debated topic. As an alternative to theoretical models of visual search that propose sequences of separate serial or parallel stages of processing, we suggest a queueing processing structure that entails a serial transition between parallel processing stages. We develop a continuous-time queueing model for standard visual search tasks to formalize and implement this notion. Specified as a finite-time, single-line, multiserver queueing system, the model accounts for both accuracy and response time (RT) data in visual search on a distributional level. It assumes two stages of processing. Visual stimuli first go through a massively parallel preattentive stage of feature encoding. They wait if necessary and then enter a limited-capacity attentive stage serially where multiple processing channels (“servers”) integrate features of several stimuli in parallel. A core feature of our model is the serial transition from the unlimited-capacity preattentive processing stage to the limited-capacity attentive processing stage. It enables asynchronous attentive processing of multiple stimuli in parallel and is more efficient than a simple chain of two successive, strictly parallel processing stages. The model accounts for response errors by means of two underlying mechanisms, namely, imperfect processing of the servers and, in addition, incomplete search adopted by the observer to maximize search efficiency under an accuracy constraint. For statistical inference, we develop a Monte-Carlo-based parameter estimation procedure, using maximum likelihood (ML) estimation for accuracy-related parameters and minimum distance (MD) estimation for RT-related parameters. We fit the model to two large empirical data sets from two types of visual search tasks. The model captures the accuracy rates almost perfectly and the observed RT distributions quite well, indicating a high explanatory power. The number of independent parallel processing channels that explain both data sets best was five. We also perform a Monte-Carlo model uncertainty analysis and show that the model with the correct number of parallel channels is selected for more than 90% of the simulated samples.

Massively Parallel Modeling of Battery Energy Storage Systems for AC/DC Grid High-Performance Transient Simulation

Extensive integration of power electronics apparatuses complicates the modern power grid and consequently necessitates time-domain transients study for its planning and operation. In this work, a heterogeneous computing architecture utilizing the CPU and graphics processing unit (GPU) is proposed for the efficient study of interactions between a power grid network and massive utility-scale battery energy storage systems (BESSs). The device-level electromagnetic transient (EMT) simulation aiming at enhanced fidelity of the BESS is conducted simultaneously with electro-mechanical transient stability (TS) simulation which suffices system-level dynamic security assessment. Since the reservation of a large amount of energy storage units is computationally intensive for the CPU, the concurrent multi-streaming, multi-threading capability of GPU is exploited to achieve asynchronous sequential-parallel processing, so that the proposed EMT-TS co-simulation can flexibly harness all available computing resources. The multi-rate scheme is adopted for further computational burden alleviation in addition to achieving timely information exchange. It shows that the heterogeneous computation of an IEEE 118-bus system integrated with a substantial number of distributed batteries becomes feasible following the achievement of a remarkable speedup of over 200, and the device- as well as system-level accuracy are validated by MATLAB/Simulink^® and DSATools^TM/TSAT simulation, respectively.

Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications

Burst-Mode (BM) formalism is a variant of an asynchronous Finite State Machine (FSM) that operates in ‘burst-mode’ timing assumption and offers simple entry into asynchronous circuit design. However, some of BM’s well-formedness properties, while useful for implementing BM specifications as circuits, are rather restrictive in some important contexts e.g. BM’s maximal set property (or its analog, Extended Burst-Mode (XBM) formalism’s distinguishability constraint) forbids non-deterministic specifications that are inherent in some design approaches, input and output bursts must alternate meaning BMs are not a proper extension of FSMs with arcs labelled by single events, and BMs cannot express input-output concurrency whereas FSMs can with interleaving. The latter limitation is particularly problematic when interoperability between several formalisms is desirable. In this paper, we propose the Burst Automation (BA) model that is more powerful and yet simpler than BM, by relaxing BM’s well-formedness properties. BA is a proper extension of FSMs, and can express input-output concurrency and non-determinism. We define BA’s interleaving semantics via its asynchronous reachability graph that is an FSM, and develop three translations from BAs to Signal Transition Graphs (STGs) that preserve strong bisimulation, weak bisimulation, or the language. Former two translations may be exponential, whereas latter translation is linear. The resulting STG can then be used for verification and synthesis into Speed-Independent (SI) or Quasi-Delay-Insensitive (QDI) circuits, or for composition with other STGs. The proposed workflow was implemented in Workcraft, and experimental results show an improved synthesis rate and a significant reduction in the literal count.

Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits

In recent times, synchronous circuits are facing design related issues like clock skew, glitch power, EMI, leakage power, etc. The clock-less design paradigm – Asynchronous design challenges most of these issues and accepted as a better alternative to clocked circuits. QDI based Null Convention Logic (NCL) is such a clock-less design concept. However, NCL designs couldn’t get wide spread acceptance due to unavailability of commercial CAD tools and design compatible NCL standard cell library. The proposed research work in this paper demonstrates design and characterization of FinFET based NCL cell library to facilitate QDI based asynchronous circuit design. The NCL cells are designed with ASAP 7nm PDK. A complete set of 27 NCL threshold gates are developed and characterized in cadence using ocean scripting. Various time and energy models are extracted for different process corners using EDA platform. The proposed work will help research scholars to implement NCL based asynchronous circuits. This paper also demonstrates comparative performance analysis of bulk-CMOS and multi-gate FinFET based NCL threshold gates in 16 nanometer technology. The analysis has concluded average 19% of improvement in power-delay produce for FinFET based cells compared to its CMOS counterparts. To showcase two-dimensional comparison, various static and semi-static NCL gate structures are also compared in term of their power and speed. Various arithmetic circuits are designed using these standard NCL cells to demonstrate its application. The results indicated substantial performance improvement in terms of power and speed.

Key factors for designing and delivering an effective asynchronous professional learning experience

In this paper, we explore the key factors for designing and delivering an effective asynchronous professional learning experience. This research study was developed with 107 participants in a module of a Postgraduate Certificate in Academic Practice (PGCAP) - a qualification which is offered to new academics at a United Kingdom (UK) Russell Group university, in line with practice at many other UK higher education institutions (HEIs). The module design was led by a range of factors which the relevant literature deems important for ensuring successful asynchronous online learning design. A questionnaire was created to measure participants’ overall perceptions regarding efficiency (learning context, facilitation, tutor feedback, peer feedback) and gains (presence, participation, persistence, connectedness, sense of community, learning experience). Participants were also invited to refer to the extent to which peer collaboration contributed to learning, to how far they felt part of a community on the module and to whether the asynchronous learning approach facilitated learning. Our results both confirmed and contradicted the positive findings of the literature: respectively, our participants did indeed find that many of the asynchronous design factors led, for them, to successful learning; they also identified some of the factors (e.g., peer feedback) as more challenging. We discuss the results of our study in terms of the effectiveness of this range of factors, considering the specific context of our module; we raise relevant questions about the issues and dilemmas involved in designing and delivering asynchronous learning courses when participants have a dual role as both learners and teachers.

Synthesis of the Structure of a Computer System Functioning in Residual Classes

An important task of designing complex computer systems is to ensure high reliability. Many authors investigate this problem and solve it in various ways. Most known methods are based on the use of natural or artificially introduced redundancy. This redundancy can be used passively and/or actively with (or without) restructuring of the computer system. This article explores new technologies for improving fault tolerance through the use of natural and artificially introduced redundancy of the applied number system. We consider a non-positional number system in residual classes and use the following properties: independence, equality, and small capacity of residues that define a non-positional code structure. This allows you to: parallelize arithmetic calculations at the level of decomposition of the remainders of numbers; implement spatial spacing of data elements with the possibility of their subsequent asynchronous independent processing; perform tabular execution of arithmetic operations of the base set and polynomial functions with single-cycle sampling of the result of a modular operation. Using specific examples, we present the calculation and comparative analysis of the reliability of computer systems. The conducted studies have shown that the use of non-positional code structures in the system of residual classes provides high reliability. In addition, with an increase in the bit grid of computing devices, the efficiency of using the system of residual classes increases. Our studies show that in order to increase reliability, it is advisable to reserve small nodes and blocks of a complex system, since the failure rate of individual elements is always less than the failure rate of the entire computer system.

Maize root behavior as three-inputs-three-outputs logical gates due to positive gravitropism and nutritropism

Root growth and their interactions can provide valuable information for the development of asynchronous logic systems. Here, maize root behavior due to positive gravitropism and nutritropism is evaluated as three-inputs-three-outputs logical gates. Using plant roots as the element for unconventional computing, the Boolean functions of each root tropism were constructed through arithmetic-logical operations. One gravity gate (rGG) and two nutrient gates (rNG1 and rNG2) were fabricated using additive manufacturing. The rGG platform was oriented with roots directly pulled down by gravity which computes (x, y, z) = (xz + yz, x + y¯z+yz¯, xy + yz), whereas specific output channels in rNG1 and rNG2 were fertigated with high phosphorus concentration resulting in (x, y, z) = (x + y + z, xy + xz, xyz) for rNG1 and (x, y, z) = (xyz, xy¯z+xyz¯, x + y + z) for rNG2. For rGG, rNG1, and rNG2, the symbols x, y, and z pertain to “root presence” in the related channel, whereas top bar on the symbols indicates “root absence”. Anatomical traits of roots were evaluated to assess possible differences in vascular tissues due to gravitropic and nutritropic responses. Overall, maize primary roots showed prominent positive gravitropism and nutritropism, and the roots that were most attracted by gravitational or nutritional stimuli showed an increase in the diameter of phloem and xylem. The logic exhibited by roots was dependent on the gravitropic and nutritropic stimuli to which they were exposed in the different logic gates. The responsiveness of maize roots to environmental stimuli such as gravity and nutrients provided valuable information to be used in computational bioelectronics.

1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS

We have developed a full-digital wired-logic DNN processor that is 5.3 times smaller and 2.6 times more energy efficient than previously developed processors. Our processor is capable of inferring a MNIST classification task with 90.6% accuracy and 1.2 nJ of energy per classification at 3.89 Mfps. We also developed a neuron and synapse-saving neural network using nonlinear neural network technology to reduce the number of processing elements to be implemented. Lastly, we developed a logical compression technique for area and energy-saving neuron cell circuits. Using these techniques, we devised a digital asynchronous wired-logic DNN processor.

Calculation of reliability indicators of asynchronous circuits

The problems are considered. The calculation of the main reliability indicators of asynchronous circuits within the framework of the theory of reliability is performed: failure rate, gamma-percentage time to failure and time to failure. Information on the reliability of similar elements of commercially produced asynchronous circuits, including reliability indicators, depending on the impact of accelerating factors (temperature, electric mode) and circuit manufacturing technology is used as initial data. On the basis of the results obtained, graphs of the failure rate dependence for asynchronous circuits from the operating time are constructed. Keywords asynchronous scheme, reliability, failure, reliability indicator

Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits

Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits

TomocuPy - efficient GPU-based tomographic reconstruction with asynchronous data processing.

Fast 3D data analysis and steering of a tomographic experiment by changing environmental conditions or acquisition parameters require fast, close to real-time, 3D reconstruction of large data volumes. Here a performance-optimized TomocuPy package is presented as a GPU alternative to the commonly used central processing unit (CPU) based TomoPy package for tomographic reconstruction. TomocuPy utilizes modern hardware capabilities to organize a 3D asynchronous reconstruction involving parallel read/write operations with storage drives, CPU-GPU data transfers, and GPU computations. In the asynchronous reconstruction, all the operations are timely overlapped to almost fully hide all data management time. Since most cameras work with less than 16-bit digital output, the memory usage and processing speed are furthermore optimized by using 16-bit floating-point arithmetic. As a result, 3D reconstruction with TomocuPy became 20-30 times faster than its multi-threaded CPU equivalent. Full reconstruction (including read/write operations and methods initialization) of a 20483 tomographic volume takes less than 7 s on a single Nvidia Tesla A100 and PCIe 4.0 NVMe SSD, and scales almost linearly increasing the data size. To simplify operation at synchrotron beamlines, TomocuPy provides an easy-to-use command-line interface. Efficacy of the package was demonstrated during a tomographic experiment on gas-hydrate formation in porous samples, where a steering option was implemented as a lens-changing mechanism for zooming to regions of interest.

An Extended Spatiotemporal Contextual Learning and Memory Network Model for Hardware Implementation

A spatiotemporal contextual learning and memory network (STCLMN) model was proposed based on the hippocampal CA1 network using the difference equations suitable for digital computer simulations. However, the inherent capability of handling and processing of continuous-time asynchronous signals (spikes) cannot be fully employed in the STCLMN model. Furthermore, digital circuit implementation of the STCLMN is not suitable for real-time edge applications, wherein small size, low power consumption, and real-time learning capability are necessary. Therefore, this study extends the original STCLMN model using a set of differential equations to overcome the above problems encountered by STCLMN for asynchronous circuit implementation. The minimum accuracy required for a compact and low-power hardware implementation of the proposed model is then investigated. The validity and feasibility of the proposed model are confirmed through numerical simulations and experiments with a small mixed analog/digital circuit based on the investigated accuracy. In this study, LIF neurons are used because of their ease of circuit implementation. The proposed eSTCLMN model would enable an efficient circuit implementation of an asynchronous spiking neural network with spatiotemporal contextual one-shot learning and memory.

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

ANFIS multi-tasking algorithm implementation scheme for ball-on-plate system stabilization

This paper presents the design and realization of a ball-on-plate system using a 3-degree-of-freedom parallel robot controlled by an adaptive neuro-fuzzy in-ference system. The ball-on-plate system is nonlinear, multivariable, with an under-actuated feature. Initially, the parallel robot is designed using SolidWorks and mechanized using a computer numerical control machine. Followed by the presentation of the ball-on-plate system mathematical model and the simplified model obtained. Afterwards, the inverse kinematics are performed to derive the appropriate angle for each servomotor. Eventually, the controller is designed and implemented in a double loop feedback scheme. A comparison between the proposed controller and a conventional proportional–integral–derivative controller in terms of time response, overshoot, and steady-state error is carried out. Furthermore, a comparison between sequential and asynchronous parallel processing is conducted for two different scenarios. The first scenario is when moving the ball to the origin while the second is for disturbance rejection. Simulation and experimental results show that the adaptive neuro-fuzzy inference system implemented using asynchronous parallel processing improves the real-time system stability by considerably decreasing oscillations as well as enhancing the ball movement smoothness with a small stead-state error.

Arquitecturas Pipeline Asincrónicas Register Less NULL Convention Logic (RL-NCL) Usando Puertas Básicas

Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it’s low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (NCL). The pipeline is a very common technique used in digital circuits to achieve high throughput. Although one can implement a pipeline using NCL gates, recent works have shown that register-less pipelines are possible using modified NCL gates. In this paper we propose two new Register-Less NCL (RL-NCL) pipeline architectures and two new methods to design NCL gates, which can be implemented even in Field Programmable Gate Arrays (FPGAs) or using the standard cells method. The new design of the proposed architecture was able to achieve an average area reduction of 27,32%, an average latency reduction of 14,1% and an average throughput increase of 5,54% comparing with the conventional NCL pipeline architecture.