Burst Automaton: Framework for Speed-Independent Synthesis Using Burst-Mode Specifications

Abstract

Burst-Mode (BM) formalism is a variant of an asynchronous Finite State Machine (FSM) that operates in ‘burst-mode’ timing assumption and offers simple entry into asynchronous circuit design. However, some of BM’s well-formedness properties, while useful for implementing BM specifications as circuits, are rather restrictive in some important contexts e.g. BM’s maximal set property (or its analog, Extended Burst-Mode (XBM) formalism’s distinguishability constraint) forbids non-deterministic specifications that are inherent in some design approaches, input and output bursts must alternate meaning BMs are not a proper extension of FSMs with arcs labelled by single events, and BMs cannot express input-output concurrency whereas FSMs can with interleaving. The latter limitation is particularly problematic when interoperability between several formalisms is desirable. In this paper, we propose the Burst Automation (BA) model that is more powerful and yet simpler than BM, by relaxing BM’s well-formedness properties. BA is a proper extension of FSMs, and can express input-output concurrency and non-determinism. We define BA’s interleaving semantics via its asynchronous reachability graph that is an FSM, and develop three translations from BAs to Signal Transition Graphs (STGs) that preserve strong bisimulation, weak bisimulation, or the language. Former two translations may be exponential, whereas latter translation is linear. The resulting STG can then be used for verification and synthesis into Speed-Independent (SI) or Quasi-Delay-Insensitive (QDI) circuits, or for composition with other STGs. The proposed workflow was implemented in Workcraft, and experimental results show an improved synthesis rate and a significant reduction in the literal count.