Non-volatile Memory Technologies Research Articles

Pathways to efficient neuromorphic computing with non-volatile memory technologies

Historically, memory technologies have been evaluated based on their storage density, cost, and latencies. Beyond these metrics, the need to enable smarter and intelligent computing platforms at a low area and energy cost has brought forth interesting avenues for exploiting non-volatile memory (NVM) technologies. In this paper, we focus on non-volatile memory technologies and their applications to bio-inspired neuromorphic computing, enabling spike-based machine intelligence. Spiking neural networks (SNNs) based on discrete neuronal “action potentials” are not only bio-fidel but also an attractive candidate to achieve energy-efficiency, as compared to state-of-the-art continuous-valued neural networks. NVMs offer promise for implementing both area- and energy-efficient SNN compute fabrics at almost all levels of hierarchy including devices, circuits, architecture, and algorithms. The intrinsic device physics of NVMs can be leveraged to emulate dynamics of individual neurons and synapses. These devices can be connected in a dense crossbar-like circuit, enabling in-memory, highly parallel dot-product computations required for neural networks. Architecturally, such crossbars can be connected in a distributed manner, bringing in additional system-level parallelism, a radical departure from the conventional von-Neumann architecture. Finally, cross-layer optimization across underlying NVM based hardware and learning algorithms can be exploited for resilience in learning and mitigating hardware inaccuracies. The manuscript starts by introducing both neuromorphic computing requirements and non-volatile memory technologies. Subsequently, we not only provide a review of key works but also carefully scrutinize the challenges and opportunities with respect to various NVM technologies at different levels of abstraction from devices-to-circuit-to-architecture and co-design of hardware and algorithm.

Resistance switching in two-terminal ferroelectric-semiconductor lateral heterostructures

Developing new memory concepts and devices has been one of the most productive fields of research for the past decade. There is a need for a nonvolatile memory technology based on resistance switching. An ideal memory element is a bistable rectifying diode that enables realization of a simple crossbar memory array with highest areal bit density. Ferroelectrics have been suggested to code digital information due to their intrinsic and stable binary electronic polarization. However, realization of a ferroelectric bistable rectifying diode is challenging since ferroelectricity and electrical conductivity are mutually exclusive and cannot coexist in a single compound. As a solution, lateral ferroelectric-semiconductor heterostructures have been suggested for the realization of ferroelectric diodes. Bistable rectifying diodes and their respective nonvolatile crossbar memory arrays based on ferroelectric-semiconductor lateral heterostructures have been successfully demonstrated with organic ferroelectrics and organic semiconductors. The present review focuses on the resistance switching in ferroelectric-semiconductor heterostructure rectifying diodes based on polymers and discusses the latest developments over the last decade.

(Invited) Reliability and Scaling Perspectives of HfO2-Based OxRAM

Hafnium oxide OxRAM (Oxide Random Access Memory) is a non-volatile memory technology that has been widely investigated over the last 15 years. Its working mechanism relies on the formation and rupture of a tiny conductive filament through a HfO2 layer sandwiched between an active (Ti) and inert (TiN) electrodes. This causes the electrical resistance to very over three orders of magnitudes between a low resistance state (LRS) and a high resistance state (HRS).OxRAM is a strong candidate to replace embedded Flash technology at scaled nodes. This is justified by several considerations but mainly driven by the low cost of integration and very high compatibility with standard CMOS technology. Yet OxRAM faces tremendous challenges in terms of reliability, variability and scaling.In this paper we first show our latest findings in terms of reliability on a Ti/HfO2(5nm)/TiN cell. Controlling LRS and HRS resistance distributions can be achieved with a proper write/erase algorithm design (see Fig. 1) and it is a key point to enable large array integration. A proper write/erase sequence ensures long bit endurance up to 107 cycles. Data retention is then evaluated at four different temperatures (125, 165, 200 and 260 °C) to extract a 10 years retention temperature of 85°C.Next, we discuss OxRAM scaling perspectives. In this context, it is essential to take into account both the resistive cell and its selector (most typically a MOS transistor). As recently shown [2], so far the OxRAM scaling has been mainly limited by the programming current, which determines the MOS selector size. Even if the OxRAM cell is integrated in the BEOL above its selector, the bitcell size is mostly determined by the underlying transistor. In addition, the OxRAM programming voltage dictates the transistor EOT and challenges the transistor reliability for scaled nodes. We demonstrated our OxRAM cell integration with a thin gate oxide FDSOI transistor (GO1/SG) and we show how this paves the OxRAM integration in a 28nm node.Eventually we discuss the ultimate scaling perspective of an OxRAM array in a Cross-Point architecture. To enable such architecture the development of a BEOL selector is mandatory and we focused on Ovonic Threshold Switching device (OTS) for this scope. The OTS works switching between a low-conductive state and a metastable conductive one, which is voltage-triggered. We demonstrated (see Fig. 3) a 1S1R (one selector one resistor) OxRAM cell where the HfO2 memory is co-integrated with a series Ge-Sb-Se-N (GSSN) OTS. We eventually discuss the limits of this architecture showing that a trade-off exists between the half pitch of the Cross-Point array metal lines and the size of the memory bank.REFERENCE[1] G. Sassine et al., 2018 IEEE International Reliability Physics Symposium (IRPS). [2] J. Sandrini et al., 2019 IEEE Electronic Device Meeting (IEDM). [3] D. Alfaro Robayo et al., 2019 IEEE 11th International Memory Workshop (IMW). Figure 1

Sage

Non-volatile main memory (NVRAM) technologies provide an attractive set of features for large-scale graph analytics, including byte-addressability, low idle power, and improved memory-density. NVRAM systems today have an order of magnitude more NVRAM than traditional memory (DRAM). NVRAM systems could therefore potentially allow very large graph problems to be solved on a single machine, at a modest cost. However, a significant challenge in achieving high performance is in accounting for the fact that NVRAM writes can be much more expensive than NVRAM reads. In this paper, we propose an approach to parallel graph analytics using the Parallel Semi-Asymmetric Model (PSAM) , in which the graph is stored as a read-only data structure (in NVRAM), and the amount of mutable memory is kept proportional to the number of vertices. Similar to the popular semi-external and semi-streaming models for graph analytics, the PSAM approach assumes that the vertices of the graph fit in a fast read-write memory (DRAM), but the edges do not. In NVRAM systems, our approach eliminates writes to the NVRAM, among other benefits. To experimentally study this new setting, we develop Sage , a parallel semi-asymmetric graph engine with which we implement provably-efficient (and often work-optimal) PSAM algorithms for over a dozen fundamental graph problems. We experimentally study Sage using a 48--core machine on the largest publicly-available real-world graph (the Hyperlink Web graph with over 3.5 billion vertices and 128 billion edges) equipped with Optane DC Persistent Memory, and show that Sage outperforms the fastest prior systems designed for NVRAM. Importantly, we also show that Sage nearly matches the fastest prior systems running solely in DRAM, by effectively hiding the costs of repeatedly accessing NVRAM versus DRAM.

(Invited) Some Recent Progress in Ferroelectric Memory Technology

Ferroelectric memory, based on the persistent remnant polarization of certain ferroelectric materials that are switchable by an appropriate applied field, has rekindled tremendous interest ever since the discovery of HfO2-base ferroelectrics [1], and both the one-transistor-one-capacitor (1T1C) based ferroelectric random-access memory (FeRAM) and the single-transistor (1T) based ferroelectric-gated field-effect-transistor (FeFET) variety have made significant progress. In this paper, we will review some of the important progress that we have made in both areas, while standing on the shoulders of other previous contributors, starting with the FeRAM technology below.The cell structure of FeRAM is similar to that of a DRAM structure, except that the storage capacitor is replaced by a ferroelectric one, leading to the possibility of nonvolatility without the need for a power-hungry refresh operation of the DRAM. Because of challenges concerning CMOS compatibility, physical thickness scalability, and inability to build 3D ferroelectric capacitors, the traditional perovskite-based ferroelectric materials (such as PZT and SBT) have prevented the FeRAM cell size from further scaling down beyond the 130-nm technology node, which has confined the current FeRAM products to very limited niche markets [1]. The introduction of hafnium oxide (HfO2)-based ferroelectrics has turned out to be a game changer, as high-quality and scalable ferroelectric capacitors have since been reported, including TiN/Al:HfO2/TiN-based 3D deep-trench capacitors [1]. Among various doped and even undoped HfO2 ferroelectric thin films, the HfxZr1-xO2 system has attracted extra attention because of its wide composition range and relatively low processing temperature (<= 400 0C), making it potentially compatible with Back-End-of-Line (BEOL) process [1]. Here we will present the results of our study on a leading foundry’s BEOL-processed Hf0.5Zr0.5O2-based ferroelectric capacitors over a wide range of areas (10-2 to 103 µm2) on 12-in wafers. Some critical issues, including wake-up behavior, endurance, retention, size dependence, temperature dependence, and uniformity across the wafers have all been systematically characterized and will be discussed, as well as their potential for automotive applications at elevated temperatures.More coverage of this talk will be focused on FeFET cells made by the same foundry using their conventional front-end CMOS process except for the ferroelectric gate stack of the MOS transistor. It should be noted that the FeFET cell structure was proposed decades ago but failed to commercialize primarily because of the retention problem associated with the traditional perovskite-based ferroelectric materials [2,3]. The relatively short retention time of those perovskite-based ferroelectric FeFETs , although cannot meet the requirements of nonvolatile memory technology, is more than adequate for DRAM applications. And a 1-T ferroelectric DRAM technology based on FeFETs, named FEDRAM, was proposed [4,5]. One major attraction of the HfO2-based FeFET is its significantly longer retention. In this talk, we will discuss the underlying mechanisms contributing to the retention loss, including the presence of the depolarization field and gate leakage followed by trapping [2]. Moreover, we will present the reason why the FeFET cell based on the ferroelectric HfO2 can achieve better retention time compared with those based on PZT and SBT [6]. While the HfO2-based FeFETs have demonstrated impressive memory retention, they are suffering from limited endurance. We will discuss the causes of such reliability concerns [7]. It will be shown that the endurance failure is mainly attributed to the charge trapping and trap generation in the gate stack, rather than fatigue of polarization in the HfO2 ferroelectric layer. The understanding of the mechanisms behind the retention loss and the endurance issues will help us to formulate possible strategies for further advancing the pathway toward commercialization of the FeFET memory technology.The nearly identical memory cell structure as well as the similar program/erase algorithm between FeFET and NAND-Flash memory naturally leads to the concept of 3D ferroelectric memory stacks based on FeFET cells, as proposed by the Yale group [8]. This patented 3D memory technology will also be briefly discussed.This work was supported by the National Science Foundation (NSF) under Award No: 1609162.

Hotspot-Aware Hybrid Memory Management for In-Memory Key-Value Stores

Emerging Non-Volatile Memory (NVM) technologies promise much higher memory density and energy efficiency than DRAM, at the expense of higher read/write latency and limited write endurance. Hybrid memory systems composed of DRAM and NVM have the potential to provide very large capacity of main memory for in-memory key-value (K-V) stores. However, there remains challenges to directly deploy DRAM-based K-V stores in hybrid memory systems. The performance and energy efficiency of K-V stores on hybrid memory systems have not been fully explored yet. In this paper, we propose HMCached , an in-memory K-V store built on a hybrid DRAM/NVM system. HMCached utilizes an application-level data access counting mechanism to identify frequently-accessed (hotspot) objects (i.e., K-V pairs) in NVM, and migrates them to fast DRAM to reduce the costly NVM accesses. We also propose an NVM-friendly index structure to store the frequently-updated portion of object metadata in DRAM, and thus further mitigate the NVM accesses. Moreover, we propose a benefit-aware memory reassignment policy to address the slab calcification problem in slab-based K-V store systems, and significantly improve the benefit gain from the DRAM. We implement the proposed schemes with Memcached and evaluate it with Zipfian-like workloads. Experiment results show that HMCached significantly reduces NVM accesses by 70 percent compared to the vanilla Memcached running on a DRAM/NVM hybrid memory system without any optimizations, and improves application performance by up to 50 percent. Moreover, compared to a DRAM-only system, HMCached achieves 90 percent of performance and 46 percent reduction of energy consumption for realistic (read-intensive) workloads while significantly reducing the DRAM usage by 75 percent.

Nonvolatile Memory Cell Based on Memristor

Memristor, one of the fundamental circuit elements, has promising applications in non-volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.

External Sorting Algorithm: State-of-the-Art and Future Directions

The advent of the era of big data provides new opportunities and more challenges to sorting algorithms. The traditional internal sorting algorithm cannot adapt to the explosive growth of data, and the memory cannot accommodate all the data for sorting, so the external sorting algorithm arises at the historic moment. Because of the different application scenarios, storage devices and improvement strategies, there are many kinds of external sorting algorithms. Traditional main memory architecture based on DRAM faces the problems of capacity, energy consumption and reliability. Emerging nonvolatile memory technologies are non-volatile, high-density, byte-addressable, low-power, so they can replace persistent storage, main memory or storage class memory. Though NVM devices provide new choices to the revolution of traditional memory and storage system, traditional external sorting algorithms cannot achieve its performance. This paper first sorts out the development of external sorting algorithm, and summarizes it into four kinds of external sorting algorithm based on HDD, embedded device, SSD and NVM. In addition, the classical external sorting algorithms based on different storage devices are listed, and our opinions are put forward. Finally, this paper proposes three problems that need to be solved urgently in the future development of external

Effects of magnetic field on resistive switching in multiferroic based Ag/BiFeO3/FTO RRAM device

We report the effects of the magnetic field on resistive switching behavior in the Ag/BiFeO3/FTO RRAM device through conventional I–V characteristics. The switching of the device from a high resistance state (HRS) to a low resistance state (LRS) at a certain threshold voltage (Vt) evidences a shift under the magnetic influence. The shifting of Vt toward higher voltage is due to the appearance of the Lorentz force and magnetoelectric effect when the magnetic field is applied perpendicular to the flow of current. The resistance of the HRS and LRS increases simultaneously under the application of the magnetic field due to the induced Hall resistance effect. The OFF/ON ratio∼12, which is repeatable for 100 multiple cycles. The discrete RESET state of the device is achieved by pulse-width and pulse-height modulation. Substantially, the resistance of these states increases systematically under the action of the magnetic field. The control of resistance states with the pulse-height and magnetic field in Ag/BiFeO3/FTO shows promise for future multilevel non-volatile memory technology.

Physical chemistry of the TiN/Hf0.5Zr0.5O2 interface

Ferroelectric hafnia-based thin films are promising candidates for emerging high-density embedded nonvolatile memory technologies, thanks to their compatibility with silicon technology and the possibility of 3D integration. The electrode–ferroelectric interface and the crystallization annealing temperature may play an important role in such memory cells. The top interface in a TiN/Hf0.5Zr0.5O2/TiN metal–ferroelectric–metal stack annealed at different temperatures was investigated with X-ray photoelectron spectroscopy. The uniformity and continuity of the 2 nm TiN top electrode was verified by photoemission electron microscopy and conductive atomic force microscopy. Partial oxidation of the electrode at the interface is identified. Hf is reduced near the top interface due to oxygen scavenging by the top electrode. The oxygen vacancy (VO) profile showed a maximum at the top interface (0.71%) and a sharp decrease into the film, giving rise to an internal field. Annealing at higher temperatures did not affect the VO concentration at the top interface but causes the generation of additional VO in the film, leading to a decrease of the Schottky Barrier Height for electrons. The interface chemistry and n-type film doping are believed to be at the origin of several phenomena, including wake-up, imprint, and fatigue. Our results give insights into the physical chemistry of the top interface with the accumulation of defective charges acting as electronic traps, causing a local imprint effect. This may explain the wake-up behavior as well and also can be a possible reason of the weaker endurance observed in these systems when increasing the annealing temperature.

True Random Number Generation From Commodity NVM Chips

In this article, we propose a novel technique to generate true random numbers (TRNs) using off-the-shelf non-volatile memory (NVM) chips. In particular, we illustrate a TRN generator (TRNG) extraction methodology from two types of NVM technologies: 1) emerging resistive NVM, and 2) charge-based NOR flash. We exploit the variability in programming latency while performing write and erase operations. The main causes of such effects can be attributed to the switching-time variability of the NVM devices and second-order effects, such as peripheral CMOS variability and circuit parasitics. Through multiple experiments, we show that dominant variability contribution arises from NVM switching-time distributions. In order to increase the quality of randomness, we propose an XOR-based post-processing technique. In the proposed methodology, latency values are first extracted from multiple locations on the chip followed by the application of post-processing technique. The randomness of the generated bitstream is evaluated using NIST SP 800-22 statistical test suite, and all the 15 tests are passed with encouraging P-values. We validated the proposed NVM-based TRNG for a wide range of operational temperatures (−40 °C to +85 °C). Utilization of the existing NVM chips and no requirement of additional specialized hardware make the proposed TRNG technique highly advantageous and cost-effective.

ICELIA: A Full-Stack Framework for STT-MRAM-Based Deep Learning Acceleration

A large variety of applications rely on deep learning to process big data, learn sophisticated features, and perform complicated tasks. Utilizing emerging non-volatile memory (NVM)'s unique characteristics, including the crossbar array structure and gray-scale cell resistances, to perform neural network (NN) computation is a well-studied approach in accelerating deep learning applications. Compared to other NVM technologies, STT-MRAM has its unique advantages in performing NN computation. However, the state-of-the-art research have not utilized STT-MRAM for deep learning acceleration due to its device- and architecture-level challenges. Consequently, this paper enables STT-MRAM, for the first time, as an effective and practical deep learning accelerator. In particular, it proposes a full-stack framework iCELIA spanning multiple design levels, including device-level fabrication, circuit-level enhancements, architecture-level synaptic weight quantization, and system-level accelerator design. The primary contributions of iCELIA over our prior work CELIA include a new non-uniform weight quantization scheme and much enhanced accelerator system design. The proposed framework significantly mitigates the model accuracy loss due to reduced data precision in a cohesive manner, constructing a comprehensive STT-MRAM accelerator system for fast NN computation with high energy efficiency and low cost.

NV-Journaling: Locality-Aware Journaling Using Byte-Addressable Non-Volatile Memory

Modern file systems rely on the journaling mechanism to maintain crash consistency. The use of non-volatile memory (NVM) significantly improves the performance of journaling file systems. However, the superior performance of NVM will increase the likelihood of the journal filling up more often, thereby increasing the frequency of checkpointing. Together with the large amount of random checkpointing I/O found in most use cases, the checkpointing process becomes a new performance bottleneck. This paper proposes NV-Journaling, a strategy that reduces the frequency of checkpointing as well as reshapes the I/O pattern of checkpointing from one of random I/O to that which is more sequential I/O. NV-Journaling introduces fine-grained commits along with a cache-friendly NVM journaling layout that exploits the idiosyncrasies of NVM technology. Under this scheme, only the modified portion of a block, rather than the entire block, is written into the NVM journal device. Doing so significantly reduces checkpoint frequency and achieves better space utilization. NV-Journaling further reshapes the I/O pattern of checkpoint using a locality-aware checkpointing process. Checkpointed blocks are classified into hot and cold blocks. NV-Journaling maintains a hot block list to absorb repeated updates, and a cold bucket list to group blocks by their proximity on disk. When a checkpoint is required, cold buckets are selected such that blocks are sequentially flushed to the hard disk. We built a prototype of NV-Journaling by modifying the JBD2 layer in the Linux kernel and evaluated it using different workloads. Our experimental results show that NV-Journaling can improve performance by up to 4.3× compared to traditional journaling.

RangeKV: An Efficient Key-Value Store Based on Hybrid DRAM-NVM-SSD Storage Structure

Persistent key-value (KV) stores are an integral part of storage infrastructure in data centers. Emerging non-volatile memory (NVM) technologies are potential alternatives for future memory architecture design. In this study, we use NVM to optimize the KV store and propose RangeKV, an LSM-tree based persistent KV store built on a heterogeneous storage architecture. RangeKV uses RangeTab in NVM to manage L0 data and increases L0 capacity to reduce the number of LSM tree levels and system compactions. RangeKV pre-constructs the hash index of RangeTab data to reduce NVM access times and adopts a double-buffer structure to reduce LSM-tree write amplification due to compactions. We implement RangeKV based on RocksDB and conduct a comparative test and performance evaluation with RocksDB and NoveLSM. The test results show that the overall random write throughput is improved by $4.5\times $ to $5.7\times $ compared to RocksDB. In addition, RangeKV has a significant performance advantage over NoveLSM.

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM

Spin Torque Transfer Magnetic RAM (STT-MRAM) is a promising Non-Volatile Memory (NVM) technology achieving high density, low leakage power, and relatively small read/write delays. It provides a solution to improve the performance and to mitigate the leakage power consumption compared to SRAM-based processors. However, the process heterogeneity and the sophisticated back-end-of-line (BEOL) structure make it difficult to integrate the STT-MRAM in two-dimensional integrated circuits (2D ICs). In this article, we implement a RISC-V-based processor with STT-MRAM using a heterogeneous 3D integration methodology. Compared with the SRAM-based 2D counterpart, the MRAM-based 3D IC provides up to 17.55 percent silicon area saving, together with either 34.74 percent performance gain or 13.90 percent energy reduction.

A Latency-Optimized and Energy-Efficient Write Scheme in NVM-Based Main Memory

Nonvolatile memory (NVM) technologies are promising candidates as the next-generation main memory due to high scalability and low energy consumption. However, the performance bottlenecks, such as high write latency and low cell endurance, still exist in NVMs. To address these problems, frequent pattern compression schemes have been widely used, which however suffer from the lack of flexibility and adaptability. In order to overcome these shortcomings, we propose a well-adaptive NVM write scheme, called dynamic frequent pattern compression (DFPC), to significantly reduce the amount of write units and extend the lifetime. Instead of only using static frequent patterns in existing FPC schemes, which are predefined and not always efficient for all applications, the idea behind DFPC is to exploit the characteristics of data distribution in execution to obtain dynamic patterns, which often appear in the real-world applications. To further improve the compression ratio, we exploit the value locality in a cache line to extend the granularity of dynamic patterns. Hence, DFPC can encode the contents of cache lines with more kinds of frequent data patterns. Moreover, to further support efficient write and read operations in the context of multilevel/triple-level cell NVMs, we need to extend the DFPC to improve performance in terms of the access latency and energy consumption. We hence propose a latency-optimized and energy-efficient compression write scheme to encode the compressed data with low energy and latency states, i.e., enhanced DFPC, thus reducing the latency and energy consumption. We implement DFPC in GEM5 with NVMain and execute the applications from SPEC CPU2006 to evaluate our scheme. Experimental results demonstrate the efficacy and efficiency of DFPC. We have released the source codes for public use at Github https://github.com/dfpcscheme/DFPCScheme .

Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing

Low-power smart devices are becoming pervasive in our world. Thus, relevant research efforts are directed to the development of innovative low power computing solutions that enable in-memory computations of logic-operations, thus avoiding the von Neumann bottleneck, i.e., the known showstopper of traditional computing architectures. Emerging non-volatile memory technologies, in particular Resistive Random Access memories, have been shown to be particularly suitable to implement logic-in-memory (LIM) circuits based on the material implication logic (IMPLY). However, RRAM devices non-idealities, logic state degradation, and a narrow design space limit the adoption of this logic scheme. In this work, we use a physics-based compact model to study an innovative smart IMPLY (SIMPLY) logic scheme which exploits the peripheral circuitry embedded in ordinary IMPLY architectures to solve the mentioned reliability issues, drastically reducing the energy consumption and setting clear design strategies. We then use SIMPLY to implement a 1-bit full adder and compare the results with other LIM solutions proposed in the literature.

Non-volatile memory technology for IoT

Non-volatile memory technology for IoT

SMART: A Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

The storage industry is moving toward emerging non-volatile memories (NVMs), including the spin-transfer torque magnetoresistive random-access memory (STT-MRAM) and the phase-change memory (PCM), owing to their high density and low-power operation. In this paper, we demonstrate, for the first time, circuit models and performance benchmarking for the domain wall (DW) reversal-based magnetoelectric-antiferromagnetic random access memory (ME-AFMRAM) at cell-level and at array-level. We also provide perspectives for coherent rotation-based memory switching with topological insulator-driven anomalous Hall read-out. In the coherent rotation regime, the ultra-low power magnetoelectric switching coupled with the terahertz-range antiferromagnetic dynamics result in substantially lower energy-per-bit and latency metrics for the ME-AFMRAM compared to other NVMs including STTMRAM and PCM. After characterizing the novel ME-AFMRAM, we leverage its unique properties to build a dense, on-chip, secure NVM platform, called SMART: A Secure Magnetoelectric Antiferromagnet- Based Tamper-Proof Non-Volatile Memory. New NVM technologies open up challenges and opportunities from a data-security perspective. For example, their sensitivity to magnetic fields and temperature fluctuations, and their data remanence after power-down make NVMs vulnerable to data theft and tampering attacks. The proposed SMART memory is not only resilient against data confidentiality attacks seeking to leak sensitive information but also ensures data integrity and prevents Denial-of-Service (DoS) attacks on the memory. It is impervious to particular power side-channel (PSC) attacks which exploit asymmetric read/write signatures for 0 and 1 logic levels, and photonic side-channel attacks which monitor photo-emission signatures from the chip backside.

Persistency semantics of the Intel-x86 architecture

Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance of RAM. To describe the persistency guarantees of NVM, several memory persistency models have been proposed in the literature. However, the persistency semantics of the ubiquitous x86 architecture remains unexplored to date. To close this gap, we develop the Px86 (‘persistent x86’) model, formalising the persistency semantics of Intel-x86 for the first time. We formulate Px86 both operationally and declaratively, and prove that the two characterisations are equivalent. To demonstrate the application of Px86, we develop two persistent libraries over Px86: a persistent transactional library, and a persistent variant of the Michael–Scott queue. Finally, we encode our declarative Px86 model in Alloy and use it to generate persistency litmus tests automatically.