(Invited) Reliability and Scaling Perspectives of HfO2-Based OxRAM

Abstract

Hafnium oxide OxRAM (Oxide Random Access Memory) is a non-volatile memory technology that has been widely investigated over the last 15 years. Its working mechanism relies on the formation and rupture of a tiny conductive filament through a HfO2 layer sandwiched between an active (Ti) and inert (TiN) electrodes. This causes the electrical resistance to very over three orders of magnitudes between a low resistance state (LRS) and a high resistance state (HRS).OxRAM is a strong candidate to replace embedded Flash technology at scaled nodes. This is justified by several considerations but mainly driven by the low cost of integration and very high compatibility with standard CMOS technology. Yet OxRAM faces tremendous challenges in terms of reliability, variability and scaling.In this paper we first show our latest findings in terms of reliability on a Ti/HfO2(5nm)/TiN cell. Controlling LRS and HRS resistance distributions can be achieved with a proper write/erase algorithm design (see Fig. 1) and it is a key point to enable large array integration. A proper write/erase sequence ensures long bit endurance up to 107 cycles. Data retention is then evaluated at four different temperatures (125, 165, 200 and 260 °C) to extract a 10 years retention temperature of 85°C.Next, we discuss OxRAM scaling perspectives. In this context, it is essential to take into account both the resistive cell and its selector (most typically a MOS transistor). As recently shown [2], so far the OxRAM scaling has been mainly limited by the programming current, which determines the MOS selector size. Even if the OxRAM cell is integrated in the BEOL above its selector, the bitcell size is mostly determined by the underlying transistor. In addition, the OxRAM programming voltage dictates the transistor EOT and challenges the transistor reliability for scaled nodes. We demonstrated our OxRAM cell integration with a thin gate oxide FDSOI transistor (GO1/SG) and we show how this paves the OxRAM integration in a 28nm node.Eventually we discuss the ultimate scaling perspective of an OxRAM array in a Cross-Point architecture. To enable such architecture the development of a BEOL selector is mandatory and we focused on Ovonic Threshold Switching device (OTS) for this scope. The OTS works switching between a low-conductive state and a metastable conductive one, which is voltage-triggered. We demonstrated (see Fig. 3) a 1S1R (one selector one resistor) OxRAM cell where the HfO2 memory is co-integrated with a series Ge-Sb-Se-N (GSSN) OTS. We eventually discuss the limits of this architecture showing that a trade-off exists between the half pitch of the Cross-Point array metal lines and the size of the memory bank.REFERENCE[1] G. Sassine et al., 2018 IEEE International Reliability Physics Symposium (IRPS). [2] J. Sandrini et al., 2019 IEEE Electronic Device Meeting (IEDM). [3] D. Alfaro Robayo et al., 2019 IEEE 11th International Memory Workshop (IMW). Figure 1