Smart Logic-in-Memory Architecture for Low-Power Non-Von Neumann Computing

Tommaso Zanotti,Paolo Pavan,Francesco Maria Puglisi

doi:10.1109/jeds.2020.2987402

Abstract

Low-power smart devices are becoming pervasive in our world. Thus, relevant research efforts are directed to the development of innovative low power computing solutions that enable in-memory computations of logic-operations, thus avoiding the von Neumann bottleneck, i.e., the known showstopper of traditional computing architectures. Emerging non-volatile memory technologies, in particular Resistive Random Access memories, have been shown to be particularly suitable to implement logic-in-memory (LIM) circuits based on the material implication logic (IMPLY). However, RRAM devices non-idealities, logic state degradation, and a narrow design space limit the adoption of this logic scheme. In this work, we use a physics-based compact model to study an innovative smart IMPLY (SIMPLY) logic scheme which exploits the peripheral circuitry embedded in ordinary IMPLY architectures to solve the mentioned reliability issues, drastically reducing the energy consumption and setting clear design strategies. We then use SIMPLY to implement a 1-bit full adder and compare the results with other LIM solutions proposed in the literature.

Highlights

The Internet of Things (IoT) is promoting the spreading of battery powered smart devices in many sectors, from the industry, to improve the efficiency of industrial processing, to the healthcare, to monitor patients from distance, and in many others
Resistive Random Access Memories (RRAM) are a promising candidate for Logic-in-Memory (LIM) applications, as they are non-volatile storing elements which at the same time can act as computing element in logic gates [4], [5]
OPERATION SCHEME To solve the issues of the ordinary IMPLY, we proposed a novel LIM smart scheme, i.e., [14]

Summary

INTRODUCTION

The Internet of Things (IoT) is promoting the spreading of battery powered smart devices in many sectors, from the industry, to improve the efficiency of industrial processing, to the healthcare, to monitor patients from distance, and in many others. Its functionality has been explored in many simulation works [9]–[11], and recently experimentally demonstrated [5], [12] Encouraging, this scheme is affected by many severe issues such as the logic state degradation [9]–[10], [13]–[14] and the strong sensitivity to driving voltage variations [13]–[14], which can prevent the correct circuit functionality if not considered during the design phase. We simulate the performance of a 1-bit full adder using the and IMPLY schemes on a RRAM array and compare the results with other state-of-the-art LIM solutions

RRAM COMPACT MODEL FOR RELIABLE CIRCUIT DESIGNS

SIMPLY OPERATION SCHEME

IMPLY VS SIMPLY

CONCLUSION