Device-circuit co-design of logic-in-memory circuits using a physics-based RRAM compact model

Abstract

Logic-in-memory architectures based on resistive random access memory (RRAM) technology and the material implication (IMPLY) logic are a promising solution for the development of energy efficient computing hardware for edge computing applications. However, RRAM devices nonidealities, such as cycle-to-cycle variability and random telegraph noise, and circuit-related issues such as logic state degradation, strongly affect the reliability of these circuits and complicate their design. In this, work we use a physics-based RRAM compact model which reproduces the effect of device nonidealities (i.e., variability, Random Telegraph Noise, self-heating) and that was calibrated on three RRAM technologies from the literature to study the reliability and performance of a conventional and a recently proposed smart IMPLY architectures. Finally, we underline the importance of the physics-based RRAM compact model as a tool for implementing device-circuit co-design strategies.