Nonvolatile Memory Cell Research Articles

Ferroelectric-Gated Nanoelectromechanical Nonvolatile Memory Cell

A ferroelectric-gated nanoelectromechanical (NEM) nonvolatile random-access memory cell [negative capacitance (NC)-NEM memory] is proposed and investigated. By adjusting the structural parameters of the NEM relay, the pull-in voltage of the NC-NEM memory cell can be reduced, and its pull-out voltage can even become negative. Hence, an NEM relay with a ferroelectric layer in the gate stack can be used as a nonvolatile random-access memory cell. Herein, the device design and operational principles for read/program/erase are introduced in detail. The program/erase voltage and the program delay time of the NC-NEM memory cell have been quantitatively estimated.

Fast and reliable storage using a 5 bit, nonvolatile photonic memory cell

Optically storing and addressing data on photonic chips is of particular interest as such capability would eliminate optoelectronic conversion losses in data centers. It would also enable on-chip non-von Neumann photonic computing by allowing multinary data storage with high fidelity. Here, we demonstrate such an optically addressed, multilevel memory capable of storing up to 34 nonvolatile reliable and repeatable levels (over 5 bits) using the phase change material Ge2Sb2Te5 integrated on a photonic waveguide. Crucially, we demonstrate for the first time, to the best of our knowledge, a technique that allows us to program the device with a single pulse regardless of the previous state of the material, providing an order of magnitude improvement over previous demonstrations in terms of both time and energy consumption. We also investigate the influence of write-and-erase pulse parameters on the single-pulse recrystallization, amorphization, and readout error in our multilevel memory, thus tailoring pulse properties for optimum performance. Our work represents a significant step in the development of photonic memories and their potential for novel integrated photonic applications.

Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms

Neural networks (NNs) have become the go-to tool for solving many real-world recognition and classification tasks with massive and complex data sets. These networks require large data sets for training, which is usually performed on GPUs and CPUs in either a cloud or edge computing setting. No matter where the training is performed, it is subject to tight power/energy and data storage/transfer constraints. While these issues can be mitigated by replacing SRAM/DRAM with nonvolatile memories (NVMs) which offer near-zero leakage power and high scalability, the massive weight updates performed during training shorten NVM endurance and engender high write energy. In this paper, an NVM-friendly NN training approach is proposed. Weight update is redesigned to reduce bit flips in NVM cells. Moreover, two techniques, namely, filter exchange and bitwise rotation, are proposed to respectively balance writes to different weights and to different bits of one weight. The proposed techniques are integrated and evaluated in Caffe. Experimental results show significant power savings and endurance improvements, while maintaining high inference accuracy.

Hot-Spot Suppression for Resource-Constrained Image Recognition Devices With Nonvolatile Memory

Resource-constrained devices with convolutional neural networks (CNNs) for image recognition are becoming popular in various Internet of Things and surveillance applications. They usually have a low-power CPU and limited CPU cache space. In such circumstances, nonvolatile memory (NVM) has great potential to replace DRAM as main memory to improve overall energy efficiency and provide larger main-memory space. However, due to the iterative access pattern, performing CNN-based image recognition may introduce some write hot-spots on the NVM main memory. These write hot-spots may lead to reliability issues due to limited write endurance of NVM. In order to improve the endurance of NVM main memory, this paper leverages the CPU cache pinning technique and exploits the iterative access pattern of CNN to resolve the write hot-spot effect. In particular, we present a CNN-aware self-bouncing pinning strategy to minimize the maximal write cycles in NVM cells by proactively fastening CPU cache lines, so as to effectively suppress the write hot-spots to NVM main memory with limited performance degradation. The proposed strategy was evaluated by a series of intensive experiments and the results are encouraging.

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. This study describes a compiler optimization technique to overcome such disadvantages of a nonvolatile memory component in hybrid cache memories. A hybrid cache is proposed to overcome the disadvantages using a compiler. Specifically, to minimize the number of write operations for nonvolatile memory, we present a data replacement technique that considers the locations of the register spill data. Many portions of the memory accesses are yielded by the spill data of a register allocator in an optimizing compiler. Such spill data can be partially removed using a recalculation method. Thus, we implemented an optimization technique that rearranges the data placement with recalculation to minimize the write instructions on the nonvolatile memory. Our experimental results show that the proposed technique can reduce the average number of spill codes by 20%, and improves the energy consumption by 20.2% on average.

Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption

In this paper, we propose an energy-efficient reconfigurable platform for in-memory processing based on novel four-terminal spin Hall effect-driven domain wall motion devices that could be employed as both nonvolatile memory cell and in-memory logic unit. The proposed designs lead to unity of memory and logic. The device to system level simulation results show that, with 28% area increase in memory structure, the proposed in-memory processing platform achieves a write energy ~15.6 fJ/bit with 79% reduction compared to that of SOT-MRAM counterpart while keeping the identical 1 ns writing speed. In addition, the proposed in-memory logic scheme improves the operating energy by 61.3%, as compared with the recent nonvolatile in-memory logic designs. An extensive reliability analysis is also performed over the proposed circuits. We employ advanced encryption standard (AES) algorithm as a case study to elucidate the efficiency of the proposed platform at application level. Simulation results exhibit that the proposed platform can show up to 75.7% and 30.4% lower energy consumption compared to CMOS-ASIC and recent pipelined domain wall (DW) AES implementations, respectively. In addition, the AES energy-delay product can show 15.1% and 6.1% improvements compared to the DW-AES and CMOS-ASIC implementations, respectively.

A new multitime programmable non-volatile memory cell using high voltage NMOS

A new multitime programmable (MTP) non-volatile memory (NVM) cell using high voltage NMOS is proposed. A PMOS transistor is used for programming, erasing, and reading, and a high voltage NMOS is used for selecting the memory cell. The memory cell has fewer number of transistors and terminals compared with the typical conventional memory cell. This reduces the area consumption and simplifies the implementation of memory's external circuit. In addition, the subthreshold swing (SS) of the memory cell is improved for larger coupling ratio. Experimental investigation on transfer characteristics, endurance, retention, and threshold voltage VTH shift and leakage current of the high voltage NMOS of the memory cell are presented. The experimental endurance behaviour of the proposed memory cell is superior to the conventional memory cell.

Studying ReRAM devices at Low Earth Orbits using the LabOSat platform

LabOSat (acronym for “Laboratory On a Satellite”) is a type of electronic platform designed to perform experiments in harsh, remote environments. Up to now, LabOSat platforms have been used mainly for characterizing and validating custom and commercial electronic devices at Low Earth Orbits (LEO). Many of these platforms are running experiments aboard ÑuSat satellites, which are built and operated by Argentine company Satellogic. A brief description of LabOSat platforms is presented here, along with details of their validation both at LEO and at a nuclear reactor. The electrical characterization of custom non-volatile memory cells — as performed by a LabOSat platform at LEO — is also described, and the results of such experiment are compared with results obtained on Earth. The memory cells studied were TiO2-based and La1/3Ca2/3MnO3-based ReRAM devices.

LEO: Low Overhead Encryption ORAM for Non-Volatile Memories

Data confidentiality attacks utilizing memory access patterns threaten exposure of data in modern main memories. Oblivious RAM (ORAM) is an effective cryptographic primitive developed to thwart access-pattern-based attacks in DRAM-based systems. However, in emerging non-volatile memory (NVM) systems, the increased writes due to encryption of multiple data blocks on every Path ORAM (state-of-the-art efficient ORAM) access impose significant energy, lifetime, and performance overheads. LEO ( L ow overhead E ncryption O RAM ) is an efficient Path ORAM encryption architecture that addresses the high write overheads of ORAM integration in NVMs, while providing security equivalent to the baseline Path ORAM. LEO reduces NVM cell writes by securely decreasing the number of block encryptions during the write phase of a Path ORAM access. LEO uses a secure, two-level counter mode encryption framework that opportunistically eliminates re-encryption of unmodified blocks, reducing NVM writes. Our evaluations show that on average, LEO decreases NVM energy by 60 percent, improves lifetime by 1.51 $\times$ , and increases performance by 9 percent over the baseline Path ORAM.

Field-Free Programmable Spin Logics via Chirality-Reversible Spin-Orbit Torque Switching.

Spin-orbit torque (SOT)-induced magnetization switching exhibits chirality (clockwise or counterclockwise), which offers the prospect of programmable spin-logic devices integrating nonvolatile spintronic memory cells with logic functions. Chirality is usually fixed by an applied or effective magnetic field in reported studies. Herein, utilizing an in-plane magnetic layer that is also switchable by SOT, the chirality of a perpendicular magnetic layer that is exchange-coupled with the in-plane layer can be reversed in a purely electrical way. In a single Hall bar device designed from this multilayer structure, three logic gates including AND, NAND, and NOT are reconfigured, which opens a gateway toward practical programmable spin-logic devices.

Capacity, Fidelity, and Noise Tolerance of Associative Spatial-Temporal Memories Based on Memristive Neuromorphic Networks.

We have calculated key characteristics of associative (content-addressable) spatial-temporal memories based on neuromorphic networks with restricted connectivity—“CrossNets.” Such networks may be naturally implemented in nanoelectronic hardware using hybrid memristive circuits, which may feature extremely high energy efficiency, approaching that of biological cortical circuits, at much higher operation speed. Our numerical simulations, in some cases confirmed by analytical calculations, show that the characteristics depend substantially on the method of information recording into the memory. Of the four methods we have explored, two methods look especially promising—one based on the quadratic programming, and the other one being a specific discrete version of the gradient descent. The latter method provides a slightly lower memory capacity (at the same fidelity) then the former one, but it allows local recording, which may be more readily implemented in nanoelectronic hardware. Most importantly, at the synchronous retrieval, both methods provide a capacity higher than that of the well-known Ternary Content-Addressable Memories with the same number of nonvolatile memory cells (e.g., memristors), though the input noise immunity of the CrossNet memories is lower.

Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing

This paper presents an approach to enhance floating gate quantum dot nonvolatile random access memory (QDNVRAM) cells in terms of higher-speed and lower-voltage Erase not possible with conventional floating gate nonvolatile memories. It is achieved by directly accessing the floating gate layer with a Ge quantum dot access channel via an additional drain (D2) during the Erase and/or Write operation. Quantum mechanical simulations in GeOx-cladded Ge quantum dot layers functioning as the floating gate as well access channel to facilitate Erase and Write are presented. Experimental data on fabricated long channel nonvolatile random access memory cell with SiOx-cladded Si dots is presented. Quantum simulations show lower voltage operation for GeOx-cladded Ge QD floating gate than SiOx-cladded Si dots. The Erase time is orders of magnitude faster than flash and is comparable to competing NVRAMs.

Influence of Domain Structure in Ferroelectric Substrate on Graphene Conductance (Authors' Review)

Review is devoted to the recent theoretical studies of the impact of domain structure of ferroelectric substrate on graphene conductance. An analytical description of the hysteresis memory effect in a field effect transistor based on graphene-on-ferroelectric, taking into account absorbed dipole layers on the free surface of graphene and localized states on its interfaces is considered. The aspects of the recently developed theory of p-n junctions conductivity in a graphene channel on a ferroelectric substrate, which are created by a 180-degree ferroelectric domain structure, are analyzed, and cases of different current regimes from ballistic to diffusion one are considered. The influence of size effects in such systems and the possibility of using the results for improving the characteristics of field effect transistors with a graphene channel, non-volatile ferroelectric memory cells with random access, sensors, as well as for miniaturization of various devices of functional nanoelectronics are discussed.

DNA multi-bit non-volatile memory and bit-shifting operations using addressable electrode arrays and electric field-induced hybridization

DNA has been employed to either store digital information or to perform parallel molecular computing. Relatively unexplored is the ability to combine DNA-based memory and logical operations in a single platform. Here, we show a DNA tri-level cell non-volatile memory system capable of parallel random-access writing of memory and bit shifting operations. A microchip with an array of individually addressable electrodes was employed to enable random access of the memory cells using electric fields. Three segments on a DNA template molecule were used to encode three data bits. Rapid writing of data bits was enabled by electric field-induced hybridization of fluorescently labeled complementary probes and the data bits were read by fluorescence imaging. We demonstrated the rapid parallel writing and reading of 8 (23) combinations of 3-bit memory data and bit shifting operations by electric field-induced strand displacement. Our system may find potential applications in DNA-based memory and computations.

Annealing effect on the bipolar resistive switching characteristics of a Ti/Si3N4/n-GaN MIS device

In this paper, the effect of annealing on the bipolar resistive switching characteristics of a Ti/Si3N4/n-GaN metal-insulator-semiconductor (MIS) structure memristor is demonstrated. The results show that the stability and repeatability of the bipolar resistive switching are greatly improved in annealed Ti/Si3N4/n-GaN MIS devices. The mechanism involved is revealed by both conductive force microscopy (CFM) and x-ray photoelectron spectroscopy (XPS). It is confirmed to in-situ local Ti doping in Si3N4 by thermal annealing and can be ascribed to the local Ti dopants in the Si3N4 bonding the N atoms at positive bias by electro-reductive process that benefits to form stable nanoscale Si filaments. On the contrary, the Si filaments rupture by recombining with N atoms near the n-GaN side at negative bias. The proposed device is apt to integrate with a GaN-based high electron mobility transistor (HEMT) to structure a one-transistor-one-resistor (1T1R) nonvolatile memory cell, which is expected to develop the application of the nitride semiconductors in data storage in addition to the applications in light-emitting diodes, laser diodes, power devices, and photodetectors.

Dedicated channels

Researchers in the US have presented quantum dot floating gate non-volatile random access memories (QD-NVRAMs) with significantly faster erase times than the state-of-the-art. Their employed technique also improves device reliability and general performance while saving space. Here, we take a closer look at their work and at the history and development of quantum dot technology. Research into quantum dot non-volatile memory began two decades ago following the demonstration of site-specific self-assembly of 4–6 nm diameter silicon nanodots. In 2004, this was followed by theoretical study of the tunnelling rate from the inversion channel to the dots in a floating gate. The next stage was to fabricate a quantum dot channel field-effect transistor, which was achieved in 2011. However, it wasn't until 2016 that actual QD-NVRAM devices, incorporating all of these processes, were realised. Experimental ID-VG characteristics of a QD-NVRAM showing the stored charge retrieval via quantum dot access channel through the source terminal. Inset shows the 3-D schematic with four layers of quantum dots (top two layers forming the quantum dot access channel and the bottom two layers serving as the floating gate). A quantum dot non-volatile memory cell with word, erase and bit lines. These non-volatile devices were hugely significant as they were compatible with CMOS processing and were fast enough to be used as cache memory as well as to replace DRAM in a microprocessor, thus saving power and area. The unique feature of QD-NVRAM cells is an access channel of quantum dots connected to a dedicated drain, which facilitates faster erasing and writing. Building on this technology, the team incorporated in their QD-NVRAMs a dedicated access channel to the floating gate region, which resulted in the aforementioned faster erase times. This was not the only advantage, however, as Faquir Jain, one of the authors of the research, explained: “The design facilitates the use of lower voltage pulses, which saves power. Also, the structure requires fewer transistors than conventional SRAMs, which reduces the overall cache area in a microprocessor. QD-NVRAM is a non-volatile memory that doesn't need continuous power like conventional SRAMs, which reduce the power consumption.” These advances mean that the QD-NVRAM can be used like an NVRAM for L2 and L3 cache memories. The reason for this, Jain said, is that “conventional NVM erase mechanisms involve removing the stored electrons in the floating gate region via the source by applying higher negative gate voltages and positive source voltage. This erase mechanism reduces the reliability and endurance of the NVM device due to tunnelling of electrons through the tunnel dielectric twice, once for writing and second for erasing, which damages the tunnel dielectric.” So, unlike conventional NVM, Jain said, “QD-NVRAM has a dedicated drain to remove the stored electrons in the QD floating gate region via QDAC, not only to enable faster erase times, but also to improve device reliability and endurance.” The immediate impact of this work will be to provide microprocessor designers with a CMOS-compatible alternative to PCM, MRAMs, and other NVRAM technologies. The long-term impact, however, should be the development of QD-NVRAMs for low power mobile processors with on-chip NVRAM memory. Therefore, now that the team has addressed the issues of CMOS incompatibility, slow erase and write times, and excess power consumption, they will refine their design by building QD-NVRAMs with smaller channel lengths, and demonstrate the integration of QD-NVRAM with logic circuits on the same chip. This technology is still in its early stages, and the work presented here may form the basis for future circuits and processers. “We envision the development of multi-bit QD-NVRAMs and their integration with quantum dot gate FETs,” said Jain, “which have exhibited multi-state characteristics. This will enable multi-valued logic designs which could help extend Moore's law using silicon CMOS technology.”

A Nonvolatile Fast-Read Two-Transistor SRAM Based on Spintronic Devices

This paper proposes a compact nonvolatile three-terminal two-transistor spintronic memory cell with a fast-read operation. It is applicable to a variety of current-driven and voltage-controlled write mechanisms, such as spin diffusion, spin Hall effect, domain wall motion, and magnetoelectric effect. Compared to the prior three-terminal spintronic memory proposal, the new cell provides 20% improvement in cell density. Compared to the conventional spin torque transfer random access memory, the proposed cell separates the read and write paths, and improves the read energy-delay product by up to $22\times $ considering process variations for transistors and MTJs.

A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-Based Neuromorphic Systems

Resistive RAM (RRAM) device has been extensively used as a scalable nonvolatile memory cell in neuromorphic systems due to its several advantages, including its small size and low-power requirements. However, resulting from the stochastic nature of the oxygen vacancies, the RRAM device suffers from reliability soft errors. In this paper, we provide for the first time a modeling framework to compute the effect of those soft errors on the system accuracy. Applying the proposed technique on a case-study system used to recognize the MNIST data set, our simulation results show that the system accuracy can degrade from 91.6% to 43% due to the RRAM reliability soft errors. To overcome this loss in the system performance, various possible adjustments to the parameters of the neuron pulses are analyzed. Furthermore, in this paper, two methodologies are proposed for automatically detecting and fixing the degradation in the system accuracy caused by the RRAM reliability soft errors. Using the suggested methodologies, the system accuracy of our case-study system can be restored back from 43% to 91.6% with small increase in the training cycle duration and with as small as 0.1% increment in the energy consumption of the system.

High-Performance Polymer Semiconductor-Based Nonvolatile Memory Cells with Nondestructive Read-Out

In this manuscript, the fabrication of polymer nonvolatile memory cells based on one-transistor–one-transistor (1T1T) device geometries is reported. A spin-coated diketopyrrolopyrrole (DPP)-based polymer semiconductor was used as the active channel layer for both the control transistor (CT) and memory transistor (MT); thermally deposited gold nanoparticles (Au NPs) were inserted between the tunneling and blocking gate dielectrics as a charge-trapping layer of the MT. In the 1T1T memory cell, the source electrode of the CT was connected to the gate electrode of the MT, while the drain electrode of the MT was connected to the gate electrode of the CT. The reading and writing processes of the memory cells operated separately, which yielded a nondestructive read-out capability. The fabricated 1T1T polymer memory cells exhibited excellent device performances with a large memory window of 16.1 V, a high programming–erasing current ratio >103, a long retention of 103 s, a cyclic stability of 500 cycles, and a 2-...

One-Transistor-One-Transistor (1T1T) Optoelectronic Nonvolatile MoS2 Memory Cell with Nondestructive Read-Out.

Taking advantage of the superlative optoelectronic properties of single-layer MoS2, we developed a one-transistor-one-transistor (1T1T)-type MoS2 optoelectronic nonvolatile memory cell. The 1T1T memory cell consisted of a control transistor (CT) and a memory transistor (MT), in which the drain electrode of the MT was connected electrically to the gate electrode of the CT, whereas the source electrode of the CT was connected electrically to the gate electrode of the MT. Single-layer MoS2 films were utilized as the channel materials in both transistors, and gold nanoparticles acted as the floating gates in the MT. This 1T1T device architecture allowed for a nondestructive read-out operation in the memory because the writing (programming or erasing) and read-out processes were operated separately. The switching of the CT could be controlled by light illumination as well as the applied gate voltage due to the strong light absorption induced by the direct band gap of single-layer MoS2 (∼1.8 eV). The resulting MoS2 1T1T memory cell exhibited excellent memory performance, including a large programming/erasing current ratio (over 106), multilevel data storage (over 6 levels), cyclic endurance (200 cycles), and stable retention (103 s).