Nonvolatile Flash Memory Research Articles

The structure and formation of non-volatile memory cells of Superflash

Split-gate embedded Flash memory technology has been around for decades and has become the standard for a wide range of devices, such as microcontrollers and smart cards. Among the, due to a number of advantages, Silicon Storage Technology Super Flash non-volatile memory technology has become the most widespread. This article presents the results of a study of the memory cells structure, examines in detail the principle of their operation and the main technological stages of the production process of forming transistor structures.

Synthesis of thienopyrazine‐ and cyclofluorene–thiophene‐based donor–acceptor low‐band gap polymers and their application in memory devices

AbstractLow‐band gap semiconductor polymer materials play a crucial role in the field of organic optoelectronics. In this context, a series of low‐band gap polymers containing thienopyrazine as the acceptor and cyclofluorene–bithiophene as the donor were synthesized and utilized in resistive random access memory (RRAM) devices. These memory devices consistently exhibit nonvolatile flash memory behavior. Remarkably, all three polymers demonstrate stability even after 1000 cycles without significant fluctuations. Notably, the three polymer‐based devices also exhibit excellent ternary memory performance, with current ratios of 1:102.8:104, 1:101.3:103.9, and 1:101.8:103.6. Furthermore, the photoelectric properties of the three polymers and the conduction mechanisms of the memory devices were thoroughly discussed.

Multifunctional polyphosphazene grafted with triphenylamine and aminostilbene chromophore for electrochromic and sensor application

In this paper, a sequence of polyphosphazenes (PPZs) as electrochromic (EC) and sensor materials have been designed and synthesized by introducing chromophores, (4-(diphenyl amino)phenyl) methanol (CH1) for PPZ1, 3-(4-(dimethyl amino) phenyl)-2-(4hydroxyphenyl) acrylonitrile (CH2) for PPZ2, and CH1 and CH2 for PPZ3 into the main chain. In terms of EC performance, PPZ1 shows the best EC performance among the three PPZs which can achieve 60 % optical contrast at 690 nm with good cyclic stability within 1000 s and fast switching response time (tcolor/tbleach = 1.2 s/0.6 s). Compared to PPZ1, the oxidation potential of PPZ3 is reduced compared to PPZ1. PPZ2 and PPZ3 as sensors are more sensitive for the detection of 2,4,6-trinitrophenol (TNP) and trifluoroacetic acid (TFA) compared to PPZ1. What's more, PPZs can be used in memory devices with non-volatile flash memory performance and switching current ratios of 103:102.4:1, 104.7:101.3:1 and 103.5.:100.6:1 respectively. Therefore, PPZs have the promising prospect in optoelectronic field.

Atomically engineered, high-speed non-volatile flash memory device exhibiting multibit data storage operations

Non-volatile memory devices, which offer large capacity and mechanical dependability as a mainstream technology, have played a key role in fostering innovation in modern electronics. Despite the advantages of non-volatile memory devices, their low ON/OFF ratio and slow operational speed have limited their performance compared to their volatile counterparts. In this study, we present a non-volatile floating-gate memory device based on van der Waals heterostructures, which exhibits ultrahigh-speed memory operations in the range of a hundred nanoseconds with an extinction ratio of up to 106. The device consists of atomically sharp interfaces between different functional elements, including atomically thin sheet of multilayer Graphene (MGr) as a floating gate, hexagonal boron nitride (h-BN) as a tunnel barrier, and two-dimensional (2D) semiconductor tin di-selenide (SnSe2) as a channel material. The memory device exhibits excellent endurance performance with stable and dependable behavior across numerous program/erase cycles, comparable to commercial volatile dynamic random access memory technology. In addition, we demonstrate the ability of the device to store multiple bits per memory cell, which offers promising potential for ultrahigh-density information storage. Our findings provide important implications for memory storage, data processing, and electronic device development, and offer new opportunities in the field of emerging 2D materials with optimal device engineering.

Double-floating-gate memory device based on energy band engineered van der Waals heterostructure

Floating-gate memory devices based on two-dimensional van der Waals heterostructures are considered as promising candidates for next-generation nonvolatile memories. Here, we report a nonvolatile double-floating-gate (DFG) memory device based on a ReS2/boron nitride/black phosphorus (BP)/boron nitride/graphene heterostructure. By comparing with a single-floating-gate device we fabricated, the device shows enlarged memory window, high on–off ratio, and improved retention performance. Based on these findings, we propose energy band diagrams showing how the memory performance can be improved by energy band engineering through designing the van der Waals heterostructure. In the DFG structure, electrons could transfer between the ReS2 channel and BP as well as between BP and graphene, providing greater controllability for electron tunneling and injection. By choosing graphene and BP as two floating gates, an energy barrier rising from the conduction-band offset between multilayer graphene and BP is set up to efficiently prevent charge leakage from the graphene floating gate and, thus, improve the memory performance. Our work demonstrates an effective way for future designs of high-performance nonvolatile flash memories.

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks.

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Nonvolatile flash memory device with ferroelectric blocking layer via in situ ALD process

To improve performances of nonvolatile charge trap flash memory devices, we propose an in situ Hf0.5Zr0.5O2 (HZO)/HfO2/Al2O3 stacked structure, which is compatible for Si with the metal–oxide–semiconductor (MOS) process based on all atomic layer deposition. Since the appropriate bandgap difference between Al2O3 and HfO2, stable charge trap operation is achieved. High-quality ferroelectric HZO film characteristics were showed by minimizing defects and Si diffusion through the sub-layer of Al2O3/HfO2. Therefore, HZO as a blocking layer enhances the memory performance of the charge trap structure due to its specific polarization effect. The proposed device has the high polarization characteristics of HZO (2Pr > 20 μ C/cm2) along with a MOS-cap window (>4 V), good retention capability (>10 years), fast program/erase response operation times (<200 μs), and strong durability (>105 cycles) while operating as a form of single level cell. By comparing Al2O3 and ferroelectric HZO as a blocking layer of the charge trap device, we confirmed that the HZO/HfO2/Al2O3 multi-layer structure had excellent characteristics according to various memory performance indicators. Our proposed high-performance charge trap flash memory can be employed in various applications, including Si-based three-dimensional structures with artificial intelligence systems.

In-Memory Computing Integrated Structure Circuit Based on Nonvolatile Flash Memory Unit

Artificial intelligence has made people’s demands for computer computing efficiency increasingly high. The traditional hardware circuit simulation method for neural morphology computation has problems of unstable performance and excessive power consumption. This research will use non-volatile flash memory cells that are easy to read and write to build a convolutional neural network structure to improve the performance of neural morphological computing. In the experiment, floating-gate transistors were used to simulate neural network synapses to design core cross-array circuits. A voltage subtractor, voltage follower and ReLU activation function are designed based on a differential amplifier. An Iris dataset was introduced in this experiment to conduct simulation experiments on the research circuit. The IMC circuit designed for this experiment has high performance, with an accuracy rate of 96.2% and a recall rate of 60.2%. The overall current power consumption of the hardware circuit is small, and the current power consumption of the subtractor circuit and ReLU circuit does not exceed 100 µA, while the power consumption of the negative feedback circuit is about 440 mA. The accuracy of analog circuits under the IMC architecture is above 93%, the energy consumption is only about 360 nJ, and the recognition rate is about 12 μs. Compared with the classic von Neumann architecture, it reduces the circuit recognition rate and power consumption while meeting accuracy requirements.

Uncovering the Role of Crystal Phase in Determining Nonvolatile Flash Memory Device Performance Fabricated from MoTe2-Based 2D van der Waals Heterostructures.

Although the crystal phase of two-dimensional (2D) transition metal dichalcogenides (TMDs) has been proven to play an essential role in fabricating high-performance electronic devices in the past decade, its effect on the performance of 2D material-based flash memory devices still remains unclear. Here, we report the exploration of the effect of MoTe2 in different phases as the charge-trapping layer on the performance of 2D van der Waals (vdW) heterostructure-based flash memory devices, where a metallic 1T'-MoTe2 or semiconducting 2H-MoTe2 nanoflake is used as the floating gate. By conducting comprehensive measurements on the two kinds of vdW heterostructure-based devices, the memory device based on MoS2/h-BN/1T'-MoTe2 presents much better performance, including a larger memory window, faster switching speed (100 ns), and higher extinction ratio (107), than that of the device based on the MoS2/h-BN/2H-MoTe2 heterostructure. Moreover, the device based on the MoS2/h-BN/1T'-MoTe2 heterostructure also shows a long cycle (>1200 cycles) and retention (>3000 s) stability. Our study clearly demonstrates that the crystal phase of 2D TMDs has a significant impact on the performance of nonvolatile flash memory devices based on 2D vdW heterostructures, which paves the way for the fabrication of future high-performance memory devices based on 2D materials.

Modulating the Performance of MoS2-Based Nanocrystal Memory via Ag Ion Implantation

Nonvolatile flash memory is an important component of the semiconductor memory device, which is widely used in a variety of portable electronic equipment. As traditional flash memory approaches its physical limit, reduced reliability and performance degradation have become unavoidable. Two-dimensional (2D) layered materials exhibit excellent electronic properties even at the atomic level and have been considered as a promising development direction for future flash memory. Here, we report a MoS2-based Ag nanocrystal memory. The fabricated memory device can form the memory stack in one step through metal ion implantation, omitting tedious deposition steps compared to the conventional process. The fabricated silver nanocrystal memory exhibits a 9 V memory window and a high ON/OFF current ratio (>107). In addition, the device also exhibits good endurance characteristics of more than 104 cycles. The ion implantation technology and the 2D nature of the channel can be used for the fabrication of flexible nanoelectronic memory devices with large-scale integration.

Light-/steam-driven polymeric crosslinking with porous multistructure pattern for ultrastable and fast-speed memory

Organic memories typically comprise memristive polymer mediums sandwiched between two electrodes, with the advantages of wet manufacturing and modulated function. However, the issues associated with structural instability, low-speed switch, and hard pattern in polymeric memories are the main obstacles towards practical uses. Here, we present an ultrastable and fast-speed memory array that uses amorphous polymer nanofilm with light-/steam-driven crosslinked porous multistructure as memristive materials. The polymer diode shows nonvolatile rewritable flash memory characteristics, with a high ON/OFF ratio, long retention time, and high speeds of set (70 ns) and reset (845 ns) operations. Impressively, the memory cell undergoes harsh conditions in ultraviolet irradiation and extreme temperatures. By rationally integrating the array with target sensors, an artificial sensory memory architecture is constructed to mimic visual/thermal perception and recording, demonstrating great potential for biomimetic neuromorphic electronics. Our results advance a commercial perspective on memristive organics capable of integration patterns and high performance.

Charge Storage and Reliability Characteristics of Nonvolatile Memory Capacitors with HfO2/Al2O3-Based Charge Trapping Layers.

Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM.

Non-volatile flash memory based on Van der Waals gate stack using bandgap tunability of hexagonal boron nitride

Electronic devices based on two-dimensional (2D) materials have extended their applications to non-volatile flash memory devices. The gate stack is a key structure in flash memory devices, and the conventional silicon-oxide-nitride-oxide-silicon (SONOS) structure has been widely applied. In this study, we propose a van der Waals (vdW) gate stack based on graphene, molybdenum disulfide (MoS2), and hexagonal boron nitride (hBN) for next-generation flash memory devices. Owing to the bandgap tunability of hBN by functionalization, hBN is capable of forming a tunneling layer, charge trap layer, and blocking layer with different bandgaps, resulting in a suitable energy band offset for program/erase operations and charge storage. This study on the vdW gate stack of MoS2/tunneling hBN/charge trap hBN/blocking hBN/graphene was carried out through technology computer-aided design (TCAD) simulation. The trapped charge density and threshold voltage (Vth) shift were investigated for different bandgaps of the hBN layers. Moreover, the pulse width and cycle were varied to reveal the charge-trapping behavior for further applications.

Non-Volatile Flash Memory on Ge With an Oxidation-Induced Self-Assembled Charge Trapping Layer

In this work, we explore the material potential of yttrium-content GeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> (YGO) in the design of a charge-trapping gate stack for embedded non-volatile memory (eNVM), which can share common gate stack materials with Ge logic CMOS. Based on a deep understanding of YGO, we propose a Ge eNVM with an oxidation-induced self-assembled YGO layer as the charge trapping layer. An eNVM fabricated on Ge offers a fast program/erase (P/E) speed (50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> and 2 ms for program and erase operations, respectively), low-voltage operation, a data retention lifetime of >10 years, and an endurance of > 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> P/E cycles.

Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors

Multi-valued logic (MVL) circuits based on heterojunction transistor (HTR) have emerged as an effective strategy for high-density information processing without increasing the circuit complexity. Herein, an organic ternary logic inverter (T-inverter) is demonstrated, where a nonvolatile floating-gate flash memory is employed to control the channel conductance systematically, thus realizing the stabilized T-inverter operation. The 3-dimensional (3D) T-inverter is fabricated in a vertically stacked form based on all-dry processes, which enables the high-density integration with high device uniformity. In the flash memory, ultrathin polymer dielectrics are utilized to reduce the programming/erasing voltage as well as operating voltage. With the optimum programming state, the 3D T-inverter fulfills all the important requirements such as full-swing operation, optimum intermediate logic value (~VDD/2), high DC gain exceeding 20 V/V as well as low-voltage operation (< 5 V). The organic flash memory exhibits long retention characteristics (current change less than 10% after 104 s), leading to the long-term stability of the 3D T-inverter. We believe the 3D T-inverter employing flash memory developed in this study can provide a useful insight to achieve high-performance MVL circuits.

Three dimensional fluorene-based polyamides facile to transfer ion designed for near-infrared electrochromic application and detection for explosive

Near-infrared electrochromic (NIR EC) functional materials are attracting increasing attention owing to their great potential for applications in smart window. However, obtaining high performance NIR EC material with high optical transmittance contrast, fast redox switching and long-term cyclic stability is still a challenge. Introducing four triphenylamine (TPA) units into one planar fluorene core to build robust three dimensional (3D) framework which not only makes ion and electron move freely but also provides sufficient space and storage sites for hosting ions will meet the requirement. Here, three kinds of new polyamides (PAs) based on conjugated fluorene as the bridge unit were designed and polycondensized by a new diamine N, N'-(9,9-bis(4-(diphenylamino)phenyl)-9H-fluorene-2,7-diyl)-bis(N-(4-methoxyphenyl) benzene-1,4-diamine), with three kinds of dicarboxylic acids to form TPAF-6F, TPAF-CA and TPAF-OA. The obtained new PAs exhibit impressive solution-processability and excellent thermal stability. Cyclic voltammograms (CV) and differential pulse voltammograms (DPV) of the PAs imply strong electronic coupling within molecule. Furthermore, the TPAF-OA film exhibits excellent EC performance with multi-coloured EC behaviour, high optical contrast (92%), high coloration efficiency (203 cm2 C−1) and outstanding cycle stability (optical contrast remains 90% over 1400 cycles) in the NIR range. TPAF-CA also shows impressive fluorescence (PL) quantum efficiency which could be used as sensor for explosive and nonvolatile flash memory properties. The strategy of introducing 3D framework block into polymer will pave a way for fabricating high performance optoelectronic devices.

Cathodoluminescence of intrinsic defects in films La : HfZrO

Lanthanum-doped (La:(HfZr)O2) nanometer films of a solid solution of hafnium oxide and zirconium oxide are of great interest for the development of a universal memory that combines an unlimited number of RAM reprogramming cycles and nonvolatile flash memory. This work is devoted to studying the cathodoluminescent properties of La : HfZrO thin films with different contents of lanthanum. It is shown that the cathodoluminescence spectra are dominated by two emission bands with intensity maxima at 2.7 and 2.2 eV. The blue band with an energy of 2.7 eV is due to an oxygen vacancy in La : HfZrO. The study of the influence of the lanthanum impurity and annealing of the samples in argon suggests that the yellow band with the emission maximum at 2.2 eV is related to the oxygen divacancy. Keywords: luminescence, hafnium oxide, zirconium oxide, oxygen vacancy.

Катодолюминесценция собственных дефектов в пленках La : HfZrO

Lanthanum-doped (La:(HfZr)O2) nanometer films of a solid solution of hafnium oxide and zirconium oxide are of great interest for the development of a universal memory that combines an unlimited number of RAM reprogramming cycles and nonvolatile flash memory. This work is devoted to studying the cathodoluminescent properties of La:HfZrO thin films with different contents of lanthanum. It is shown that the cathodoluminescence spectra are dominated by two emission bands with intensity maxima at 2.7 and 2.2 eV. The blue band with an energy of 2.7 eV is due to an oxygen vacancy in La:HfZrO. The study of the influence of the lanthanum impurity and annealing of the samples in argon suggests that the yellow band with the emission maximum at 2.2 eV is related to the oxygen divacancy.

Non-volatile memory based in-memory computing technology

By integrating the storage and computing functions on the fundamental elements, computing in-memory (CIM) technology is widely considered as a novel computational paradigm that can break the bottleneck of Von Neumann architecture. Nonvolatile memory device is an appropriate hardware implementation approach of CIM, which possess significantly advantages, such as excellent scalability, low consumption, and versatility. In this paper, first we introduce the basic concept of CIM, including the technical background and technical characteristics. Then, we review the traditional and novel nonvolatile memory devices, flash and resistive random access memory (RRAM), used in non-volatile based computing in-memory (nvCIM) system. After that, we explain the operation modes of nvCIM: in-memory analog computing and in-memory digital computing. In addition, the applications of nvCIM are also discussed, including deep learning accelerator, neuromorphic computing, and stateful logic. Finally, we summarize the current research advances in nvCIM and provide an outlook on possible research directions in the future.

New Statistical Data and Modeling of Stress-Induced Leakage Current in 3D-NAND Floating Gate Non-Volatile Flash Memories

New Statistical Data and Modeling of Stress-Induced Leakage Current in 3D-NAND Floating Gate Non-Volatile Flash Memories