Nonvolatile Flash Memory Research Articles

Statistical Investigation of Anomalous Fast Erase Dynamics in Charge Trapping NAND Flash

In nand Flash nonvolatile memories, the erase operation drives the memory cells threshold voltage toward negative values, barely representing a concern for multilevel architectures. However, during the analysis of the erase dynamics in charge trapping (CT) memory arrays using an incremental step pulse erase algorithm, it is found that a small population of memory cells ( ≈ 2%) may randomly exhibit anomalous fast erase dynamics, which causes threshold voltage fluctuations during cycling operations. The purpose of this letter is to provide a statistical characterization of this phenomenon in CT-nand Flash arrays, thus helping the comprehension of its underlying physical mechanisms.

Implementation of Product Reed Solomon Codes for Multi level cell Flash controller

In recent years, multi-level cell (MLC) flash memories have been developed as an effective solution for increasing the storage density and reducing the cost of flash memories. MLC flash memories are especially for NAND flash memories . Error control coding (ECC) is essential for correcting errors in Flash memories.In order to correct multiple random errors and burst errors, an efficient decoding algorithms are required.In this work (255, 231) Product Reed-Solomon (RS) code technique for non-volatile NAND flash memory system sare used. In this proposed code that is Product Reed Solomon can correct both multiple random errors and burst errors. The Product Reed Solomon code consists of two shortened Reed-Solomon codes and a conventional Reed- Solomon code. It can correct up to certain symbol errors. A simulation result shows that the code has improved the coding gain and low power consumption.

Professor Fujio Masuoka?s Passion and Patience Toward Flash Memory

The main feature of Flash Memory is that it can retain data when the power is shut down, which is an indispensable part of a modern electronic system. System designers benefited greatly when the electrically erased and programmed nonvolatile Flash Memory became available. DRAM has been mainly used for the main memory to store the data and program in the computer. DRAM is fast, however, it can no longer retain data when the power is shut down. It is called a volatile memory. Therefore, personal computers have external storage devices of Hard Disk Drive (HDD) at any cost. This replacement of HDD by Flash Memory has been just got started. Flash Memory has a variety of advantages; low cost, light, low power (eco-friendly), vibration free, and resistant to moisture, etc. These good points of Flash Memory have innovatively produced a digital camera, cellular phone, and removal storage card. And now, Solid State Disk (SSD) has been fed directly into a computer in the replacement of HDD.

Hindrance-functionalized π-stacked polymer based on polystyrene with pendent cardo groups for organic electronics

A hindrance-functionalized π-stacked polymer, poly(4-(9-phenyl-fluoren-9-yl)styrene) (PPFS), was designed and synthesized by the introduction of bulky 9-phenylfluorenyl moieties (PFMs) with 3D cardo structure into all the phenyl units of polystyrene (PS) through the sp3 carbon linkage. The PFMs obviously alter π-stacked conformation and interchain interactions with respect to the precursor PS. The suitable HOMO–LUMO energy gap, high triplet energy, and excellent thermal and morphological stabilities enable PPFS to serve as not only electrically bistable materials but also phosphorescent hosts. Memory devices using PPFS as an active layer exhibited nonvolatile flash memory performance with ON/OFF current ratio up to 104, high stability in retention time up to 104 s and a number of read cycles up to 105 under a read voltage of 1.5 V in both ON and OFF states, while PS based devices exhibited no memory performance. Polymer light-emitting devices (PLEDs) using PPFS as the host and FIrpic as the guest exhibited blue emission with CIE chromaticity coordinates (x, y) of (0.146, 0.349). These results indicate that hindrance-functionalization opens a way to transform commercially available general purpose polystyrenes into functional π-stacked macromolecules.

Thermally stable memory devices using graphene flakes sandwiched polymethyl methacrylate polymer layers

Fabrication and characterization of graphene flakes sandwiched polymethyl methacrylate (PMMA) hybrid bistable devices (HBD) is reported in this paper. Graphene flakes (GFs) sandwiched polymer layers were prepared through a simple solution process. The fabricated memory devices have exhibited remarkable electrical bistable behavior even at 150°C. Bistable memory behavior of the fabricated devices have been described on the basis of current-voltage characteristics. Reasonably good ON/OFF current ratio (∼103) and retention property have been obtained from the constructed memory devices. The device showed excellent stability up to 105 switching cycles without any degradation both in ON and OFF states. The results obtained have indicated that the HBD fabricated by embedding graphene flakes in an insulating polymer matrix have potential applications in organic nonvolatile flash memory devices.

Charge redistribution in a charge storage layer containing C60 molecules and organic polymers for long electron retention

A gate stack structure with an organic-polymer tunneling gate insulator on a C60-containing organic-polymer layer was developed for use as nonvolatile flash memory. Examination of the memory characteristics revealed substantial flatband voltage shifts for both electron and hole injections into C60 molecules. A long retention time was obtained for electron injection. Charge redistribution phenomena were observed in the electron retention characteristics immediately after the bias application was terminated. This proposed stack structure of organic polymers opens the door to the development of inexpensive electronic memories.

Charge storage properties of InP quantum dots in GaAs metal-oxide-semiconductor based nonvolatile flash memory devices

Metal organic vapor phase epitaxially grown 5 nm InP quantum dots (QDs) were embedded as charge storage elements between high-k control and tunneling dielectric layers in GaAs metal-oxide-semiconductor based nonvolatile memory devices. The QDs trap more electrons resulting in a large memory window (6.3 V) along with low leakage due to Coulomb blockade effect. 16.5% charge loss was found even after 105 s indicating its good charge storing potential. The programming and erasing operations were discussed with proposed band diagram.

Radically Enhanced Molecular Switches

The mechanism governing the redox-stimulated switching behavior of a tristable [2]rotaxane consisting of a cyclobis(paraquat-p-phenylene) (CBPQT(4+)) ring encircling a dumbbell, containing tetrathiafulvalene (TTF) and 1,5-dioxynaphthalene (DNP) recognition units which are separated from each other along a polyether chain carrying 2,6-diisopropylphenyl stoppers by a 4,4'-bipyridinium (BIPY(2+)) unit, is described. The BIPY(2+) unit acts to increase the lifetime of the metastable state coconformation (MSCC) significantly by restricting the shuttling motion of the CBPQT(4+) ring to such an extent that the MSCC can be isolated in the solid state and is stable for weeks on end. As controls, the redox-induced mechanism of switching of two bistable [2]rotaxanes and one bistable [2]catenane composed of CBPQT(4+) rings encircling dumbbells or macrocyclic polyethers, respectively, that contain a BIPY(2+) unit with either a TTF or DNP unit, is investigated. Variable scan-rate cyclic voltammetry and digital simulations of the tristable and bistable [2]rotaxanes and [2]catenane reveal a mechanism which involves a bisradical state coconformation (BRCC) in which only one of the BIPY(•+) units in the CBPQT(2(•+)) ring is oxidized to the BIPY(2+) dication. This observation of the BRCC was further confirmed by theoretical calculations as well as by X-ray crystallography of the [2]catenane in its bisradical tetracationic redox state. It is evident that the incorporation of a kinetic barrier between the donor recognition units in the tristable [2]rotaxane can prolong the lifetime and stability of the MSCC, an observation which augurs well for the development of nonvolatile molecular flash memory devices.

Performance Evaluation of the MOHOS Flash Memory with Fluorinated HfO2 Charge Storage Layer Using Gate Fluorine Ion Implantation

Electrical characteristics improvement of the fluorinated metal/SiO2/HfO2/SiO2/Si (MOHOS) flash memory using gate fluorine ion implantation (GFI) process has been investigated. Si-F or Hf-F bonds formation due to fluorine incorporation can reduce undesirable charges trapping and leakage path creation in the tunneling oxide, which consequently increases the program/erase (P/E) speed and endurance. Moreover, fluorinated flash memory not only enhances P/E efficiency, but also improves the data retention characteristic, which can be explained by more deep-level traps and reduced leakage path due to fluorine incorporation. P/E window closure during endurance stressing is significantly suppressed for the fluorinated flash memory, which can be also ascribed to stronger Si-F or Hf-F bonds formation within the dielectrics due to fluorine incorporation. However, the fluorinated MOHOS flash memory clearly exhibits apparent erase-saturation phenomenon due to higher electric field across on blocking oxide. The results clearly indicate the fluorinated flash memory using GFI process to simultaneously fabricate fluorinated OHO dielectrics becomes a feasible technology for future MOHOS-type nonvolatile flash memory application.

Nanoscale 2-Bit/Cell HfO$_{\bf 2}$ Nanocrystal Flash Memory

In this paper, we demonstrate 50-nm trigate nonvolatile HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocrystal memory devices on silicon-on-insulator wafers. The proposed technique, which is fully compatible with current CMOS technologies, is used to form highly localized HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> nanocrystals for application in nonvolatile flash memory. We successfully scale down conventional nonvolatile floating gate memories below the 50-nm node to achieve nanodevices for application in next-generation nonvolatile memories.

Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory

A novel stacked gated twin-bit SONOS memory for high-density nonvolatile flash memory is introduced. We introduced gated twin-bit (GTB) memory previously that has a cut-off gate and two memory nodes at a single wordline. To increase the density of the GTB memory integration, we stacked poly-silicon gates in a vertical direction. In a 4F <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^2$</tex></formula> size, we can integrate 2 N memory nodes, where N is the number of stacked gates. In this paper, its fabrication method is introduced and electrical characteristics are investigated thoroughly by device simulations.

Comparison of Fluorinated HfO2 and Si3N4 Charge Trapping Layer for Nonvolatile Flash Memories

Characteristics of fluorinated metal/SiO2/HfO2/SiO2/Si (F-MOHOS) and fluorinated metal/SiO2/Si3N4/SiO2/Si (F-MONOS) flash memory using gate fluorine ion implantation (GFI) have been investigated. Since dielectric constant of HfO2 is larger than Si3N4, electric field across on tunneling oxide of F-MOHOS flash memory is larger than F-MONOS flash memory, which results in faster program/erase speed. Moreover, HfO2 exhibits larger effective trapping density than Si3N4, which also contributes to faster program/erase speed for the F-MOHOS flash memory. Besides, charge retention of the F-MOHOS flash memory is superior than the F-MONOS flash memory, primarily due to larger conduction band offset at the HfO2/SiO2 interface (ΔEC = 1.7–2.0 eV) than at the Si3N4/SiO2 interface (ΔEC = 1.1 eV). F-MOHOS flash memory also exhibits superior program/erase endurance than F-MONOS flash memory. Therefore, F-MOHOS flash memory using GFI process is proposed to be suitable for future nonvolatile flash memory applications. On the other hand, larger dielectric constant of HfO2 inevitably induces larger electric field across on blocking oxide of F-MOHOS flash memory, then enhances electron back-tunneling from the gate electrode during erase operation, which results in obvious erase-saturation.

Conjugated polymers with cationic iridium(iii) complexes in the side-chain for flash memory devices utilizing switchable through-space charge transfer

Polycarbazole and polyfluorene containing cationic iridium(III) complexes in the side-chain have been designed and synthesized. Both polymers have been demonstrated to show conductance switching behavior and non-volatile flash memory devices based on them were successfully realized, in which the formation and dissociation of through-space charge-transfer states from the conjugated polymer “sea” to the Ir(III) complex “island”, controlled by voltage, are responsible for the conductance switching behavior and memory effect. The devices exhibit low reading, writing, and erasing voltages and a high ON/OFF current ratio. Both ON and OFF states are stable up to 107 read cycles at a read voltage of −1.0 V. Due to the different chemical structures of the polymer main-chain, the two devices show different threshold voltages. The polycarbazole derivative exhibits higher HOMO and LUMO levels compared with the polyfluorene analogue. Thus, the threshold voltage from the OFF to ON state of the device based on the polycarbazole derivative is obviously lower than that of the polyfluorene derivative-based device because of the low energy barrier between the work function of the ITO anode and the HOMO level of the polycarbazole derivative. Similarly, the threshold voltage from the ON to OFF state is evidently higher because the energy barrier of electron injection from Al into the LUMO of the polycarbazole derivative is slightly higher than that of the polyfluorene analogue. Thus, the threshold voltages of memory devices may be rationally modulated by modifying the chemical structure of polymers.

Macroscopic high density nanodisc arrays of zinc oxide fabricated by block copolymer self-assembly assisted nanoimprint lithography

We report a facile means of creating nanodisc arrays of ZnO with high densities (∼22 Gbit in−2) and narrow distributions in size, shape and periodicities (<15%) using a combination of block copolymer self-assembly and nanoimprint lithography (NIL). ZnO nanodisc arrays with sub-100 nm spatial resolutions, using high-throughput and manufacturing compatible approaches are realized. The fabrication combines benefits from the use of NIL, which is a high-throughput and repeatable tool and from the use of block copolymer self-assembly which provides for low-cost production of high-resolution NIL molds. Preliminary results of the investigation of memory performance of these arrays within MOS capacitor devices show a flat-band voltage shift of 2.53 V at a relatively low operating voltage of 10 V. A high charge trap density of 2.3 × 1018 cm−3 combined with excellent retention of ∼80% after 1000 s of discharging is observed with low tunnelling oxide thickness of 3 nm, demonstrate significant promise of the ZnO nanodiscs to act as charge storage centers in non-volatile flash memory devices.

Low-voltage driving solution-processed nickel oxide based unipolar resistive switching memory with Ni nanoparticles

Resistive random access memory (RRAM) combines the advantages of nonvolatile flash memory and volatile dynamic random access memory, avoiding their drawbacks. For the practical use of RRAM, achieving low-voltage driving is strongly desired. Here we report the effect of Ni nanoparticles on solution-processed NiO based RRAM which can realize a one diode one resistor operation by unipolar resistive switching mode and low-voltage driving for future demands. The Ni nanoparticles not only contributed to high oxygen mobility, but also affected effective insulator thickness reduction, and stoichiometric variation in NiO thin films. Furthermore, the Ni nanoparticle embedded device demonstrated good reliability. These findings can enhance the applicability of RRAM as a next generation memory device.

Electronic structure of silicon oxynitride: Ab-initio and experimental study, comparison with silicon nitride

Amorphous silicon oxide SiO2, silicon nitride Si3N4, and silicon oxynitride SiOxNy are three key dielectrics in silicon devices. Implementation of nitrided oxide (oxynitride SiOxNy) as a gate dielectric in metal-oxide-semiconductor field effect transistors has been shown to significantly improve the reliability and lifetime of devices. Also, amorphous oxynitride is used as a tunnel dielectric in nonvolatile flash memory devices. The present paper is devoted to the experimental and theoretical study of silicon oxynitride electronic structure. The ionic formula of crystalline Si2N2O is deduced from the first principles. Effective masses of charge carriers in Si2N2O are calculated and compared with experimental data on tunnel injection in amorphous SiNxOy samples. Also experimental x-ray absorption and emission spectra are compared with the theoretically calculated ones.

Graphene Gate Electrode for MOS Structure-Based Electronic Devices

We demonstrate that the use of a monolayer graphene as a gate electrode on top of a high-κ gate dielectric eliminates mechanical-stress-induced-gate dielectric degradation, resulting in a quantum leap of gate dielectric reliability. The high work function of hole-doped graphene also helps reduce the quantum mechanical tunneling current from the gate electrode. This concept is applied to nonvolatile Flash memory devices, whose performance is critically affected by the quality of the gate dielectric. Charge-trap flash (CTF) memory with a graphene gate electrode shows superior data retention and program/erase performance that current CTF devices cannot achieve. The findings of this study can lead to new applications of graphene, not only for Flash memory devices but also for other high-performance and mass-producible electronic devices based on MOS structure which is the mainstream of the electronic device industry.

Endurance Characteristics of Amorphous-InGaZnO Transparent Flash Memory With Gold Nanocrystal Storage Layer

The amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistor (TFT)-based nonvolatile transparent Flash memory devices were fabricated with gold (Au) nanocrystal storage layer. The performance and the reliability of transparent memory devices have been characterized by experiment and technology computer-aided design simulation. This memory device shows a large-enough memory window ΔV = 4.7 V at the program/erase (P/E) voltage VPGM/VERS = 35/-35 V for the P/E time TPGM/ TERS = 3/25 s. The memory window was kept almost the same after 1050 P/E cycles; however, the center voltage of the memory window (VC) was shifted in a negative direction. The cycling effect was explained by the change in the density of states (DOS) and the acceptor-like interface-trap density DitA(E) in the a-IGZO channel layer with increasing P/E cycles. The main mechanism for the change in VC was found to be the accelerated injection of holes into the gate insulator due to the energy band bending during the erase operation.

저전력과 응답시간 향상을 위한 하이브리드 하드디스크의 입출력 기법

최근 전력소모와 읽기 성능이 우수한 Solid state disk(SSD)가 많이 사용되고 있으나 가격이 고가이고 삭제 및 쓰기 연산의 효율이 낮은 것이 단점이다. 이것을 보완하기 위한 저장장치의 일종이 하이브리드 하드디스크 (H-HDD: Hybrid Hard disk drive)인데 하드디스크 내부에 플래시 메모리(NVCache: Non-volatile Cache)를 장착하여 디스크블록의 캐시로 사용한다. 본 논문에서는 H-HDD의 저전력과 응답시간을 향상시키기 위해 NVCache의 선반입 및 관리 기법을 제안한다. 제안하는 기법은 NVCache를 읽기 캐시를 위주로 사용하고 쓰기캐시는 디스크 헤드와 스핀들의 상황에 따라 쓰기 연산을 지원한다. 읽기 캐시의 경우 시간적, 지역적 지역성을 동시에 고려하여 선반입을 통해 응답시간과 전력 소모를 감소시키고 쓰기 캐시의 경우 디스크 스핀들의 동작 상태에 따라 NVCache에 쓰기를 실시하여 저전력과 응답성을 향상시키고자한다. Recently, Solid state disk is mainly used because this device has lower power consumption as well as higher response time. But it features higher price and lower performance at delete and write operations compared with HDD. To compensate this defect, Hybrid hard disk with internal non-volatile flash memory was issued. This NVCache is used as a kind of cache for disk blocks. In this paper, an I/O scheme for H-HDD is proposed for improving low power consumption as well as response time. Our method is to use this NVCache as read cache mainly and write cache when write requests are concentrated. In read cache operation, disk blocks with higher priority determined on basis of time as well as spatial localities are prefetched, which can improve response time. The write operation is conducted only at write peak time as disk spindle up costs higher battery power as well as response time. Experiments results show that the suggested method can improve response time of H-HDD and lower the power consumption.

Ion irradiation: a tool to understand oxide RRAM mechanism

Recently observed resistive random access memory (RRAM) effects in mixed oxides have opened up new horizons for a potential viable alternative to the existing flash non-volatile memory devices. Capacitor structures consisting of simple binary transition metal oxides and perovskite manganites have been shown to possess electric pulse-induced resistance switching (RS). Despite intense research activity in this area, the mechanism governing this switching remains elusive. An interesting finding common to almost all of the oxide RRAM candidate materials is their disordered bulk and/or surface structure offering better switching characteristics than their epitaxial counterpart. Swift heavy ion (SHI) irradiation was used as a unique tool to selectively create controlled defects in several oxide films possessing metal/oxide/metal-like planar structures. Using widely-investigated binary oxides, namely NiO and TiO2 thin film nanostructures, it is shown that the RS in these materials can be induced by SHI irradiation. More than 100% enhancement in the RS ratio has been achieved in these oxides. Using the online elastic recoil detection analysis, it is demonstrated that gross defects contributing to metallic filaments away from the Ag/NiO interface have a major role to play when compared with the interface effects and oxygen electromigration. The role of SHI in improving the RS in the case of TiO2 has been successfully verified. This is an attempt to show that SHI irradiation has unique qualities on offer to the modern and fast emerging field of “oxide electronics”.