Abstract
In nand Flash nonvolatile memories, the erase operation drives the memory cells threshold voltage toward negative values, barely representing a concern for multilevel architectures. However, during the analysis of the erase dynamics in charge trapping (CT) memory arrays using an incremental step pulse erase algorithm, it is found that a small population of memory cells ( ≈ 2%) may randomly exhibit anomalous fast erase dynamics, which causes threshold voltage fluctuations during cycling operations. The purpose of this letter is to provide a statistical characterization of this phenomenon in CT-nand Flash arrays, thus helping the comprehension of its underlying physical mechanisms.
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