Network-on-Chip Design Research Articles

A High Scalability Memory NoC with Shared-Inside Hierarchical-Groupings for Triplet-Based Many-Core Architecture

Innovative processor architecture designs are shifting towards Many-Core Architectures (MCAs) to meet the future demands of high-performance computing as the limits of Moore’s Law have almost been reached. Many-core processors utilize shared memory hierarchies to achieve high-speed memory systems, improving memory access efficiency. However, as the number of cores multiplies, the scalability of this system is significantly constrained by the increased proportion of long-distance and Non-Uniform Memory Access (NUMA). Improving the scalability of MCAs is crucial for achieving large/super-scale general-purpose many-core processors. This work proposes a high scalability memory Network-on-Chip (NoC) for Triplet-Based Many-Core Architecture (TriBA), named TriBA-mNoC. TriBA-mNoC maintains a consistent core-to-core spacing as the network scale increases, effectively preventing increased long-distance memory access latency. Moreover, it leverages an inherent advantage of shared-inside hierarchical-groupings, alleviating common NUMA issues in the NoC design. Evaluations of static network characteristics show that TriBA-mNoC outperforms most classical NoCs in network diameter, average distance, and cost. TriBA-mNoC can be integrated with TriBA in the same silicon die with a tile-like floorplan, forming a novel NoC called TriBA-NoC, which can combine the strengths of both networks to maximize the architecture performance. We evaluated the memory access performance and scalability of TriBA-NoC using the mathematical evaluation models and actual simulations with real traffic (PARSEC 3.0 and SPLASH-2) at different network scales. The mathematical evaluation results indicate that TriBA-NoC achieves an aggregate speedup of approximately 3x compared with 2D-Mesh for a similar number of cores. Furthermore, TriBA-NoC’s single-core speedup efficiency remains stable as the number of cores increases under the same cache hit ratio, while 2D-Mesh experiences a rapid decline, highlighting TriBA-NoC’s exceptional scalability. Finally, the actual traffic simulation results show that TriBA-NoC achieves an average memory access latency and time reduction of 25.90% − 40.50% and 5.61% − 31.69% respectively, compared with 2D-Mesh.

Network on Chip and Its Low Power Techniques

The advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques. Key Words: Network-On-Chip, System-On-Chip, latency and scalability

Design of fault tolerant algorithm for network on chip router using field programmable gate array

<p class="Abstract">Many internet protocol (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on Field programmable gate array (FPGA).</p>

Optimization of layout for embedding half hypercube into conventional tree architectures

SummaryEmbedding a graph into another graph can be utilized for structural simulation, processor allocation, and algorithm porting in the field of parallel architecture. This has the potential to enhance the physical layout of network‐on‐chip (NoC) devices as well as to investigate their virtualization possibilities. Layout is one of the many indicators of graph embedding. An optimal layout in NoC design can result in a decreased wiring area and cost, as well as the reduction in communication delay between parallel processing components. In this work, the guest graph is the half hypercube, which possess efficient routing, fault tolerance, and Hamiltonian features. The edge isoperimetric problems is solved for the half hypercube using a novel technique called the isochronal ordering. The host graphs considered in our work are complete binary trees, ‐rooted complete binary trees, and other few predominantly investigated tree based architectures.

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

<span>A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. <br /> The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. <br /> The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.</span>

DEMAP: differential evolution mapping for network on chip optimization

Network-on-chip (NoC) is a new paradigm for system-on-chip (SoC) design, which facilitates the interconnection and integration of complex components. Since this technology is still new, significant research efforts are needed to accelerate and simplify the design phases. Mapping is a critical phase in the NoC design process, as a mismatch of application software components can significantly impact the final system's performance. Therefore, it is essential to develop automated tools and methods to ensure this step. The main objective of this project is to develop a new approach that can be used to map applications on the NoC architecture to reduce communication costs. To achieve this goal, we have opted for an optimization algorithm, specifically the differential evolution algorithm.

Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip

In order to meet the complex requirements of the semiconductor market, the packet-based on-chip interconnect IP; Network-on-Chip (NoC) used in System-on-Chips (SoCs), provides provisions for in-house designers to customise the NoC design. This opens a backdoor for the adversary to insert malicious circuits to deploy attacks like exposing cryptography keys, resource depletion attacks, etc. A malicious implant, such as a Hardware Trojan (HT) on NoC that initiates a delay-of-service attack, can tamper with the system and the application performance. In this work, we model an HT that mounts a time-delay attack in a NoC by violating the path selection strategy used by the route compute unit of the adaptive NoC router. Our experimental analysis shows that the proposed HT increases the packet latency by 14.5% and degrades the system performance (IPC) by 15% over the Baseline. For HT detection, we propose a framework that uses packet traffic analysis and path monitoring to localise the HT. We also propose a security wrapper module for the route compute unit that suppresses the effect of HT with an average IPC reduction of only 1.8% over the Baseline.

Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures

Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy efficient and high performance heterogeneous NoC-based multi/many-core architectures. Because of the large and complex design space, the solution space becomes difficult to explore within a reasonable time for optimal trade-offs of energy-performance-reliability. Furthermore, reactive resource management is not effective in preventing problems from happening in adaptive systems. Therefore, in this work, we explore machine learning techniques to design and configure the NoC resources based on the learning of the system and applications workloads. Machine learning can automatically learn from past experiences and guide the NoC intelligently to achieve its objective on performance, power, and reliability. We present the challenges of NoC design and resource management and propose a generalized machine learning framework to uncover near-optimal solutions quickly. We propose and implement a NoC design and optimization solution enabled by neural networks, using the generalized machine learning framework. Simulation results demonstrated that the proposed neural networks-based design and optimization solution improves performance by 15% and reduces energy consumption by 6% compared to an existing non-machine learning-based solution while the proposed solution improves NoC latency and throughput compared to two existing machine learning-based NoC optimization solutions. The challenges of machine learning technique adaptation in multi/many-core NoC have been presented to guide future research.

Spontaneous emission noise resilience of coupled nanolasers

We investigate the spontaneous emission noise resilience of the phase-locked operation of two delay-coupled nanolasers. The system is modeled by semi-classical Maxwell–Bloch rate equations with stochastic Langevin-type noise sources. Our results reveal that a polarization dephasing time of two to three times the cavity photon lifetime maximizes the system’s ability to remain phase-locked in the presence of noise-induced perturbations. The Langevin noise term is caused by spontaneous emission processes which change both the intensity auto-correlation properties of the solitary lasers and the coupled system. In an experimental setup, these quantities are measurable and can be directly compared to our numerical data. The strong parameter dependence of the noise tolerance that we find may show possible routes for the design of robust on-chip integrated networks of nanolasers.

NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware

Neuromorphic systems are typically designed as a tile-based architecture where inter-tile data communication is facilitated using a shared global interconnect. Congestion on this interconnect can increase both interconnect energy, which increases the total energy consumption of the hardware and latency, which impacts the performance e.g., accuracy of the application that is being executed on the hardware. Mesh-based Network-on-Chip (NoC) that is used in most hardware prototypes is not the optimal interconnect solution for neuromorphic systems. This is because of the following two reasons. First, power consumption and average latency of a NoC increases exponentially with the number of tiles in the hardware. Second, a NoC cannot exploit an application’s data communication pattern efficiently. Once designed for a target hardware, the bandwidth on each NoC link stays the same, independent of the volume of data traffic between different tile pairs of the NoC. In other words, a NoC cannot be customized at a finer granularity based on an individual application running on the hardware. We show that these NoC limitations prevent opportunities to further improve energy and latency of a neuromorphic hardware. To address these limitations, we propose Dynamic Segmented Bus (SB) interconnect for neuromorphic systems. Here, a bus lane is partitioned into segments with each segment connecting a few tiles. Connection of tiles to segments and those between segments are bridged using our novel three-way segmentation switches that are programmed using the software before admitting an application to the hardware. We partition an application by analyzing its workload and place partitions intelligently onto segments. This exploits application characteristics to use the segments without any routing collisions while exploiting the latency and energy savings in the design-time mapping phase. At a high-level, our mapping algorithm places tiles that communicate the most on shorter segments utilizing fewer number of switches, thereby reducing network congestion. It can adjust the bandwidth by controlling the number of segments connected to a destination tile. At run time, our controller dynamically executes the predefined routing paths without requiring any additionally routing decisions, unlike a NoC. This allows us to improve both energy and latency. Using parallel segmented busses, our proposed interconnect architecture can support a large number of tiles without significantly increasing the design cost, energy, and latency. Simulation results show that compared to the most widely-used mesh-based NoC design, our interconnect architecture, which we call NeuSB, reduces the switch area by 20x, average interconnect energy by 6.2x, and latency by 23%.

A Machine Learning Mapping Algorithm for NoC Optimization

Network on chip (NoC) is a promising solution to the challenge of multi-core System-on-Chip (SoC) communication design. Application mapping is the first and most important step in the NoC synthesis flow, which determines most of the NoC design performance. NoC mapping has been confirmed as an NP-hard (Non-Polynomial hard) problem, which could not be solved in polynomial time. Various heuristic mapping algorithms have been applied to the mapping problem. However, the heuristic algorithm easily falls into a local optimal solution which causes performance loss. Additionally, regular topologies of NoC, such as the ring, torus, etc., may generate symmetric solutions in the NoC mapping process, which increase the performance loss. Machine learning involves data-driven methods to analyze trends, find relationships, and develop models to predict things based on datasets. In this paper, an NoC machine learning mapping algorithm is proposed to solve a mapping problem. A Low-complexity and no symmetry NoC mapping dataset is defined, and a data augmentation approach is proposed to build dataset. With the dataset defined, a multi-label machine learning is established. The simulation results have confirmed that the machine learning mapping algorithm is proposed have at least 99.6% model accuracy and an average of 96.3% mapping accuracy.

A Reliability System Evaluation Model of NoC Communication with Crosstalk Analysis from Backend to Frontend

Network on chip (NoC) is the main solution to the communication bandwidth of a multi-processor system on chip (MPSoC). NoC also brings more route requirements and is highly prone to errors caused by crosstalk. Crosstalk has become a major design problem in deep-submicron NoC communication design. Hence, a crosstalk error model and corresponding reliable system with error correction code (ECC) are required to make NoC communication reliable. In this paper, a reliability system evaluation model (RSE) of NoC communication with analysis from backend to frontend has been proposed. In the backend, a crosstalk error rate model (CER) is established with a three-wire RLC coupling model and timing constraints. The CER is used to establish functional relations between interconnect spacing, length and signal frequency, and test system reliability. In the frontend, a reliability system performance model (RSP) is established with a CER, reliability method cost and bandwidth. The RSE summarizes the frontend and backend model. In order to verify the RSE model, we propose a reliability system with a hybrid automatic repeat request technique (RSHARQ). Simulation demonstrates that the CER model is close to real circuit design. Through the CER and RSP model, the performance of RSHARQ could be simulated.

Artificial synapse topologies using arbitrary-order memristors

With the recent advances in the study of the memristive elements along with the theory of arbitrary-order calculus, a wide amount of opportunities has emerged in manufacturing and modeling of devices, as well as in the development of applications of arbitrary-order memristive circuits. This paper addresses the derivation of novel electronic bridge circuits for emulating the behavior of artificial synapses, which are the cornerstone in the design of on-chip neural networks. Bridge topologies are based on arbitrary-order memristors and can perform positive, negative and zero synaptic weights. According the characteristics and type of configuration, incremental or decremental, of each charge- or flux-controlled arbitrary-order memristor, sixty-four topologies are generated. The dynamical behavior of each memristive bridge is also derived. Features of the arbitrary-order memristive bridge synapses are investigated via simulations. The results show a significant improvement in terms of symmetry, control and update of the arbitrary-order memristive synaptic weights.

Enabling circuit-switching in modern on-chip networks

Contemporary flow control mechanisms, especially virtual channels, are employed by modern on-chip networks to allow better utilization of the link bandwidth through buffering and packet switching. Despite of being the de facto option in designs, they are also the sources of large energy footprint and long per-hop latency. On the other hand, dated and simpler flow controls such as circuit switching can draw far less power while offering an end-to-end latency analogous to wire delay. In this paper, we therefore take a further step from utilizing a single flow control mechanism within the network to allowing circuit-switching to work alongside virtual channels, which provides latency-competitive and energy-efficient on-chip network designs. Furthermore, to enable circuit switching in modern networks-on-chip, we present two independent proposals so that circuits can be formed in a network either temporally or spatially. In our evaluations, we find that both of our proposals can help achieve a very competitive latency per flit, for up to 30% lower with the temporal approach and for up to 10% lower with the spatial approach, while also dramatically suppressing the energy footprint with either approach by up to 27% and 25%, respectively.

Anticipative QoS Control: A Self-Reconfigurable On-Chip Communication.

A self-reconfigurable Network-on-Chip (NoC) architecture that supports anticipative Quality of Service (QoS) control with penetrative switch ability is proposed to enhance the performance of bidirectional-channel NoC communication while supporting prioritized packet transmission services. The anticipative QoS control not only allows each communication channel to be dynamically self-configured to transmit flits in either direction for a better channel utilization of on-chip hardware resources, but also enhances the latency performance for QoS services. The proposed anticipative control is based on penetratingly observing channel direction requests of routers that is two hops away from the current one. The added ability enables a router to allocate high-priority packets to a dedicated virtual channel and then rapidly bypass it to the next destination router. The provided flexibility of packet switch promises better channel bandwidth utilization, lower packet delivery latency, and furthermore guarantees the high-priority packets being served with a better QoS. Accordingly, in this paper, an enhanced NoC architecture supporting the hybrid anticipative QoS, penetrative switch, and bidirectional-channel control, namely Anticipative QoS Bidirectional-channel NoC (AQ-BiNoC) is presented. Tested with cycle-accurate synthetic traffic patterns, significant performance enhancement has been observed when the proposed AQ-BiNoC architecture is compared against conventional NoC designs.

Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC

The network-on-chip (NoC) is an intra-communication on the chip extended from system-on-chip (SoC). The NoC design suffers from high failure rates due to the problem of routing in the traffic conditioning. In this paper, a realistic traffic pattern is used to verify the proposed routing scheme of the NoC with the novel design topology. Here a topology named mixed-torus topology is designed with the combination of processing block and the non-processing block that has the information about the processing block, which are associated with its torus block. The designed topology is presented with the encoder application model, and the set of tasks are mapped and scheduled to the processing block by the spider monkey optimization algorithm. Then the routing of data through the non-processing block is done by the pathfinder based traffic and thermal aware adaptive routing protocol (PFTTAR), which will perform the path diversity phase and the path selection phase for better routing. The designed NoC is then treated with the statistical traffic pattern generation for the analytical study of the proposed work and is implemented in Xilinx.

Software/Hardware Co-design of 3D NoC-based GPU Architectures for Accelerated Graph Computations

Manycore GPU architectures have become the mainstay for accelerating graph computations. One of the primary bottlenecks to performance of graph computations on manycore architectures is the data movement. Since most of the accesses in graph processing are due to vertex neighborhood lookups, locality in graph data structures plays a key role in dictating the degree of data movement. Vertex reordering is a widely used technique to improve data locality within graph data structures. However, these reordering schemes alone are not sufficient as they need to be complemented with efficient task allocation on manycore GPU architectures to reduce latency due to local cache misses. Consequently, in this article, we introduce a software/hardware co-design framework for accelerating graph computations. Our approach couples an architecture-aware vertex reordering with a priority-based task allocation technique. As the task allocation aims to reduce on-chip latency and associated energy, the choice of Network-on-Chip (NoC) as the communication backbone in the manycore platform is an important parameter. By leveraging emerging three-dimensional (3D) integration technology, we propose design of a small-world NoC (SWNoC)-enabled manycore GPU architecture, where the placement of the links connecting the streaming multiprocessors (SMs) and the memory controllers (MCs) follow a power-law distribution. The proposed 3D SWNoC-enabled software/hardware co-design framework achieves 11.1% to 22.9% performance improvement and 16.4% to 32.6% less energy consumption depending on the dataset and the graph application, when compared to the default order of dataset running on a conventional planar mesh architecture.

Flexible and Efficient QoS Provisioning in AXI4-Based Network-on-Chip Architecture

We propose a network-on-chip (NoC)-based whole system design, whose communication architecture is compatible with the advanced microcontroller bus architecture advanced extensible interface 4 (AXI4) protocol and supports high-performance multiple quality-of-service (QoS) schemes. In our system, the network interface (NI) between the NoC and the master/slave node is proposed to make the NoC architecture independent from the AXI4 protocol via message format conversion between the AXI4 signal format and the packet format, offering high flexibility to the NoC design. Besides, a QoS inheritance mechanism is applied in the slave-side NI to support QoS during packets’ round-trip transfer in the NoC. The NoC system contains time-division multiplexing (TDM) and virtual channel (VC) subnetworks to apply multiple QoS schemes to AXI4 signals with different QoS tags, and the NI is responsible for signals distribution between two subnetworks. Besides, a traffic converter is proposed in each NI to balance the traffic between the two subnetworks when necessary. The experimental results show that our proposed architecture ensures a high-throughput and low-latency NoC system. By applying the traffic converter, the packet latency can be improved.

Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture

With enhancement of technology downscaling and packaging allows us to put more and more transistors within the same chip area. The Moore’s law still shows the growth in yield with increasing transistor density in deep sub-micron. This increment in transistor density encourages the computer architects to design Chip Multiprocessor (CMP) systems. In recent times, industry and researchers are focusing to add more cores per chip with increasing integration. The sharp growth in core numbers in System-on-Chip (SoC) raise intense challenges for communication among the cores. The scalability, fault tolerance and higher communication bandwidth features made Network-on-chip (NoC), a popular communication architecture than conventional bus architecture. However, the rapid shrinking of CMOS design margins in deep submicron technology has made aging mechanism such as Negative Bias Temperature Instability (NBTI), a prime concern in NoC design. In this paper, we propose a novel pre-silicon, NBTI stress aware circuit-to-system level solution for a reliable NoC router. To achieve reliability objective, we develop an NBTI aging-aware timing analysis framework based on the real workload stress. Our proposal is based on findings of most stressed path and cells due to NBTI induced effects. We develop an aging-aware cell library and used the multi Vdd technique to mitigate the NBTI induced delay effects. On the basis of volume of experimental analysis, we observed that 66.67% delay increases due to NBTI induced aging effects with real workload stress for a duration of five years. Our proposed NBTI stress mitigation algorithm and technique could able to reduce aging induced delay effects by 36%, hence enhancing the router performance under stress.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

— Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)