Network-on-Chip Design Research Articles

Performance-reliability trade-offs in short range RF power amplifier design

In this work, trade-offs between performance and reliability in CMOS RF power amplifiers at the design stage are studied. The impact of transistor sizing, amplifier class and on-chip matching network design are explored for a 130 nm technology and the implications of design decisions in transistor gate oxide reliability are discussed and projected. A strong trade-off is observed between efficiency and reliability, mainly for different on-chip output matching architectures. A comparison between two example designs is performed via SPICE simulations that include reliability models and the effects of aging on the stress conditions of each amplifier.

Optimizing FPGA-based hard networks-on-chip by minimizing and sharing resources

FPGA has become a favorable platform for Systems-on-Chip (SoC). As SoC gets larger, a Network-on-Chip (NoC) emerges as a promising solution for communication problems among SoC's modules. Consequently, the importance of NoC on FPGAs has increased, not only to solve SoC's communication problems but also as a solution to FPGA's slow interconnects and to simplify Partial Dynamic Reconfiguration (PDR). Hard NoCs have better performance and consume less area and power than Soft NoCs. However, they are not configurable and they lead to a wasted area when the network is not in use. This makes the design of hard NoCs more critical to get an optimum performance while minimizing the wasted area as much as possible. In this paper, various NoC design parameters are evaluated to find the best-fit parameters that can be used in the non-configurable hard NoC design. In addition, different router architectures are investigated to select the optimum one for hard NoCs. Moreover, an efficient novel method for embedding the hard NoC inside the FPGA is proposed. The proposed NoC reduces the wasted area by using minimum and shareable resources. The NoC provides the FPGA with a high-performance communications infrastructure at a negligible cost. A total throughput of 0.33/1.3 Tbps (at a 32/128-bit flit width) is achieved on 65 nm technology at an added cost equivalent to the area of only 16/32 logic clusters.

Inductance Extraction of Grid Power Distribution Network

For the package or on-chip power distribution network (PDN) design, plane metals are usually adopted. In this paper, we propose a closed-form grid metals solution to calculate the inductance of such grid PDN for the frequencies below its first antiresonant frequency. First, the grid PDN is equivalent to a plane PDN based on the equivalent circuit of their unit cells. Furthermore, the equivalent plane PDN is simplified as an RLCG lumped circuit, where ${L}$ is the inductance of the grid PDN. Finally, the inductance of the grid PDN is obtained by the mode analysis of the equivalent plane PDN with a modified modal function. The proposed method is scalable, which can calculate the grid PDNs with the size from micrometer to centimeter. To verify the proposed method, a centimeter grid PDN is fabricated. The inductance obtained by the proposed method has a good agreement with that obtained by measurement and 3-D full-wave simulation. The proposed method can also be expanded to the case that the grid PDN has load impedances. In comparison with the numerical methods, the proposed method can give a more easy-to-understand explanation of the new antiresonant frequency produced by the load impedance.

Elastic buffer evaluation for link pipelining under process variation

Network-on-chip (NoC) adopted for many-core intercommunications may face long link delay and power consumption limitations. A proven solution is to segment long links with storage elements or repeaters. Besides, a new design paradigm called elastic has been considered in the literature, which seems suitable for NoC designs. In this study, the authors explore the benefit of various elastic-buffer (EB) structures to be used for link pipelining. They study elastic handshaking protocols and explore various elastic buffer designed to be used in NoC era. They propose to use synchronous elastic flow (SELF) handshaking protocol for link pipelining. Results show elastic buffer structure based on SELF-handshaking protocol, which can run at least with 21% higher frequency, has 25% less delay and consumes 8% less power compared with other proposed designs. They have explored the process variation issues with various scenarios on seven different structures. They have improved the SELF-elastic buffer, which is more resilient against process variation, proposing two new structures. The new proposed structures exhibit about 5% better performance and 13% less power delay product variation in average.

A joint optimization method for NoC topology generation

The increasing demand on efficient intra-chip communication of multicore systems has driven the interconnection structure to evolve from bus/ring to Network-on-Chip (NoC). NoC design is fundamentally based on network topology generation and floorplanning. This paper proposes a joint optimization method to generate network topologies based on the floorplanning of heterogeneous IP cores for a given application-specific NoC. This method starts with clustering the heterogeneous IP cores according to their communication workloads using fuzzy clustering. It proceeds to apply a genetic algorithm to optimize the floorplanning by minimizing power consumption and/or chip area. By adding a router to each cluster of IP cores, network topologies are further generated via connecting routers based on the principles of scale-free networks. Experiments with a video processing application show that the optimized floorplanning of IP cores can be achieved by either minimizing the power consumption or chip area. An OPNET simulator is used to evaluate the performance of the NoC designed based on the proposed method. Experimental results demonstrate that the performance requirements of the application-specific NoC can be satisfied.

A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems

As programs for microprocessor architectures, network-on-chip (NoC) traffic patterns are essential tools for NoC performance assessment and design exploration. The fidelity of NoC traffic patterns has profound influence on NoC studies. In this paper, we present a systematic traffic modeling and generation methodology and a traffic suite for efficient evaluation of NoC-based many-core systems. The publicly released MCSL (multi-constraint system-level) traffic suite includes a set of realistic traffic patterns for real-world applications and covers popular NoC architectures. It captures both the communication behaviors in NoCs and the temporal dependencies among them. The MCSL traffic suite can be easily incorporated into existing NoC simulators and significantly improve NoC simulation accuracy. The proposed methodology uses formal computational models to capture both communication and computation requirements of applications. It optimizes application memory requirements, mapping, and scheduling to maximize overall system performance and utilization before extracting traffic patterns through cycle level simulations. Experiment results show that the MCSL traffic suite can be used to study NoC characteristics more accurately than traditional random traffic patterns.

Slim NoC

Emerging chips with hundreds and thousands of cores require networks with unprecedented energy/area efficiency and scalability. To address this, we propose Slim NoC (SN): a new on-chip network design that delivers significant improvements in efficiency and scalability compared to the state-of-the-art. The key idea is to use two concepts from graph and number theory, degree-diameter graphs combined with non-prime finite fields, to enable the smallest number of ports for a given core count. SN is inspired by state-of-the-art off-chip topologies; it identifies and distills their advantages for NoC settings while solving several key issues that lead to significant overheads on-chip. SN provides NoC-specific layouts, which further enhance area/energy efficiency. We show how to augment SN with state-of-the-art router microarchitecture schemes such as Elastic Links, to make the network even more scalable and efficient. Our extensive experimental evaluations show that SN outperforms both traditional low-radix topologies (e.g., meshes and tori) and modern high-radix networks (e.g., various Flattened Butterflies) in area, latency, throughput, and static/dynamic power consumption for both synthetic and real workloads. SN provides a promising direction in scalable and energy-efficient NoC topologies.

BUTHA: Boost Up Clock Terminal with Heuristic Approach for NoC

In recent days, there has been a growing interest in network-on-chip (NoC), as it offers a promising architecture for future systems on-chip (SoC). The performance degradation is the major problem in designing NoC, due to the complexity in designing a traffic generator and traffic estimator (TE) modules. In the conventional NoC design, new traffic modules and low-power algorithms (LPAS) are introduced. A LPA with an NoC has given performance degradation in the transmission rate, end-to-end delay and overall energy consumption. To address this power issue, we modeled the Menger’s theorem (MT) (graph theory (GT))-based clock boosting mechanism to produce an effective frequency for the router. The following two methods are introduced to improve the performance of NoCs: (i) development of a real-time traffic generation module and software-based traffic estimator (STE) (ii) GT approach is introduced into a dynamic frequency scaling (DFS) LPA. In general, the frequency selection process during various traffic conditions in history-based dynamic voltage scaling algorithm (HDVS) and history-based DFS algorithm (HDFS) is more complex and it gives performance degradation. In the proposed method, MT-based DFS (MT-DFS) parameters are estimated under various conditions using both 65 and 90[Formula: see text]nm TSMC CMOS technology. In comparison with conventional HDFS, the evaluations show that MT-DFS interface achieves 67.7% energy saving, 85% dynamic power savings of the links in the on-chip network and 74.27% leakage power saving of the link.

Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication

Network on chip (NoC) is the solution to solve the problem of larger system on chip and bus based communication system. NoC provides scalable, highly reliable and modular approach for on chip communication and related problems. The wireless communication technologies such as IEEE 802.15.4 Zigbee technology follow mesh, star and cluster tree topology. The paper focuses on the development of machine learning model for design and FPGA synthesis of mesh, ring and fat tree NoC for different cluster size (N = 2, 4, 8, 16, 32, 64, 128 and 256). The fat-tree based topologies incorporate more links near the root of the tree, in order to fulfill the requirement for higher communication demand closer to the root of the tree, as compared to its leafs. It is an indirect topology in which not all routers are identical in terms of number of ports connecting to other routers or elements in the network. The research article presents the use of machine learning techniques to predict the FPGA resource utilization for NoC in advance. The present study helps in NoC chip planning before designing the chip itself by taking into account known hardware design parameters, memory utilization and timing parameters such as minimum and maximum period, frequency support etc. The machine learning is carried out based on multiple linear regression, decision tree regression and random forest regression which estimate the accuracy of the design and good performance. The interprocess communication among nodes is verified using Virtex-5 FPGA, in which data flows in packets and can vary up to ‘n’ bit. The designs are developed in Xilinx ISE 14.2 and simulated in Modelsim 10.1b with the help of VHDL programming language. The developed model has been validated and has performed well on independent test data.

An Efficient Algorithm for Mapping Real Time Embedded Applications on NoC Architecture

Network-on-chip (NoC) has appeared to be an impending substitute for the communication paradigm in modern very large scale integration embedded systems. Apart from many design challenges, application mapping on the NoC system is one of the most intractable and challenging optimization problems. In this paper, we propose a hybrid, branch & bound (BB)-based exact mapping (BEMAP) algorithm, for mapping real-time embedded applications on the NoC architecture. The BEMAP optimizes the latency and throughput of the NoC system and minimizes power consumption under the bandwidth constraint. This method utilizes the modular exact and systematic search optimization techniques to obtain a multi-objective optimized solution to the mapping problem of the NoC designs. The proposed algorithm exploits the state-of-the-art BB algorithm, in order to obtain optimized results against its competitors. Experimental results under the benchmarks of several real-time embedded applications show that the proposed algorithm achieves up to 19.93% savings in power consumption and 61.10% improvement in network latency for two dimension mesh and torus topologies.

Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture

Network-on-chip (NoC) is an emerging alternative to address the communication problem in embedded system-on-chip designs. One of the key and major issues is the optimized mapping of the embedded applications on the underlined NoC platform. In this paper, we propose the bandwidth-constrained multi-objective segmented brute-force mapping (SBMAP) algorithm, which minimizes the communication energy consumption and reduces the computational complexity of the NoC designs. The algorithm generates efficient mapping of the embedded applications on the processing elements of the NoC system by segregating the application into multiple segments. It utilizes the property of modular systematic search, which produces high-performance results with optimized simulation time. We compared the SBMAP algorithm with the state-of-the-art mapping techniques, such as branch and bound (BB), near-optimal mapping (NMAP), and random mapping algorithms for mapping real-world application workloads. The experimental results validated the efficiency of the proposed algorithm against its competitors for most of the performance parameters of the NoC designs. The improvement in energy consumption of the SBMAP algorithm is up to 53% for 2-D mesh and 62% for torus topology as compared with the NMAP, BB, and random algorithms for video object plane decoder, picture in picture, Wi-Fi receiver, and multimedia system real-time application benchmarks.

Analytical Modeling of the SMART NoC

With the increasing number of components in multiprocessor systems-on-chip, standard bus based communication architectures face a formidable scalability challenge. Network-on-chip (NoC), a type of communication architecture, addresses this scalability problem by distributing the communication resources among the communicating components. A huge bottleneck to modern NoC design is its extremely slow simulation/prototyping phase. Traditionally, analytical performance models have been used to speed up this phase. However, the currently available analytical models are not applicable to state-of-the-art NoCs. This forces NoC designers to rely on simulation/prototyping. In this work, we propose an analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers. Our method registers a prediction error in network latency that is as low as 1 percent, and on an average below 2.5 and 8.4 percent, respectively, compared with the cycle-accurate GARNET network simulator and the gem5 full-system simulator running the PARSEC benchmark suite. The method also leads to two orders of magnitude speedup in computation time. It can account for variations in NoC design parameters, such as the maximum number of hops per cycle, number of virtual channels, flit size, buffer depth per virtual channel, etc. Even when these NoC design parameters are varied, our method's results remain within 5 percent of GARNET's results.

LATENCY EFFICIENT MAPPING IN 3D MESH NOC INTERCONNECTION NETWORK ARCHITECTURE

The progresses and developments in the domain of semiconductor technology is about to take us into the era where there will be thousands of cores available on a System on Chip. The onset of 3D integration technologies has unlocked the doors of novel prospects for design of on-chip networks in SoCs attaining the higher efficiency in contrast to 2D integration by aptly adjusting the increased path lengths of 2D on chip archetypes. The intelligent mapping of the applications to core on a given NoC architecture can result into the improved system’s dynamic latency. The paper presents a heuristic based on branch and bound methodology for intelligent mapping of applications to cores in 3D Mesh NoC architecture. The experimental outcomes illustrate that average latency has been immensely decreased in the optimized 3D-Mesh on chip networks when compared against optimized 2D-Mesh network of the same size.

Improved Performance of Error Controlling Codes Using Pass Transistor Logic

System-on-ship (SoC) design in the nanoelectronics era brings us not only many opportunities but also several challenges like synchronization, process uncertainty, global interconnecting delay, high scalability, and reliability. Network on Chip (NoC) could be a communication subsystem and it is rising as a revolutionary design methodology to solve the problems associated with SoC designing. Reliability is one of the major designing challenges in NoC design under technology limitations at low voltage operations and under the influence of very deep sub-micron noise sources, including crosstalk noise. To achieve the reliability of NoC, error controlling codes (ECC) are required. ECCs are broadly categorized as forward error correcting (FEC) codes and error detection codes. ECC improves the reliability of NoC with a penalty of overhead power, delay, and area. In this paper, an attempt has been made to reduce the overhead power, delay and area of FEC codes: hamming code and dual rail code, and error detecting codes: checksum and two-dimensional parity with duplication. These ECC are designed in 65 nm technology using CMOS and pass transistor logic and their power–reliability trade-off is analyzed and compared in terms of delay and overhead area. From the results, it is observed that error controlling schemes are providing the best performance with pass transistor logic over error controlling schemes with CMOS logic.

Experimental evaluation and comparison of two recent Network-on-Chip routers for FPGAs

Rapid growth in the number of Intellectual Property (IP) cores in System-on-Chip (SoC) resulted in the need for effective and scalable interconnect scheme for system components – Network-on-Chip (NoC). Router is a key component in an NoC design that impacts the overall area utilization. It is crucial to evaluate the area efficiency of NoC routers. In this paper, we evaluate and compare two recent NoC routers for Field Programmable Gated Arrays (FPGAs). The first one is generated using the automated NoC synthesis tool CONfigurable NEtwork Creation Tool (CONNECT). The second one is an NoC router manually designed using VHDL and synthesized Altera Quartus II CAD tool. Three NoC topologies namely ring, mesh and torus are used for evaluating the two routers based on area utilization metric. The routers are evaluated by varying the node sizes from 4 to 16 for each topology. For smaller NoC topologies, CONNECT router uses less area but as the NoC size increases manual router design provides up to 85% reduction in area utilization. The results presented in this paper will be useful to designers interested in NoC implementation on FPGAs.

Multicast-Aware High-Performance Wireless Network-on-Chip Architectures

Today's multiprocessor platforms employ the network-on-chip (NoC) architecture as the preferable communication backbone. Conventional NoCs are designed predominantly for unicast data exchanges. In such NoCs, the multicast traffic is generally handled by converting each multicast message to multiple unicast transmissions. Hence, applications dominated by multicast traffic experience high queuing latencies and significant performance penalties when running on systems designed with unicast-based NoC architectures. Various multicast mechanisms such as XY-tree multicast and path multicast have already been proposed to enhance the performance of the traditional wireline mesh NoC incorporating multicast traffic. However, even with such added features, the multihop nature of the wireline mesh NoC leads to high network latencies and thus limits the achievable system performance. In this paper, to sustain the high-bandwidth and high-throughput requirements of emerging applications, we propose the design of a wireless NoC (WiNoC) architecture incorporating necessary multicast support. By integrating congestion-aware multicast routing with network coding, the WiNoC is able to efficiently handle heavy multicast injections. For applications running with a broadcast-heavy Hammer cache coherence protocol, the proposed multicast-aware WiNoC achieves an average of 47% reduction in message latency compared with the XY-tree-based multicast-aware mesh NoC. This network level improvement translates into a 26% saving in full-system energy delay product.

Reliable NoC design with low latency and power consumption

Reliability has become one of the most crucial issues in network-on-chip (NoC). But how to keep low latency and power consumption when achieving reliability is still a curial challenge. A novel scheme for reliable NoCs is proposed. In the scheme, header flit is protected from router to router and data is protected from end to end. To implement the scheme, a new header protection buffer in routers is designed, which can check the timing errors and tolerate the soft errors simultaneously. Instead of checking on each router, data packet is only decoded and checked on receiver's network interface. In this way, the scheme ensures reliable transmission with low latency and power consumption. Experimental results show the feasibility of the proposed scheme in terms of power consumption, latency and area cost.

The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer

The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost. Copyright © 2017 The Institute of Electronics, Information and Communication Engineers.

CALM

With the emergence of many-core multiprocessor system-on-chips (MPSoCs), on-chip networks are facing serious challenges in providing fast communication among various tasks and cores. One promising on-chip network design approach shown in recent studies is to add express channels to traditional mesh network as shortcuts to bypass intermediate routers, thereby reducing packet latency. This approach not only changes the packet latency models, but also greatly affects network traffic behaviors, both of which have not been fully exploited in existing mapping algorithms. In this article, we explore the opportunities in optimizing application mapping for flattened butterfly, a popular express channel-based on-chip network. Specifically, we identify the unique characteristics of flattened butterfly, analyze the opportunities and new challenges, and propose an efficient heuristic mapping algorithm. The proposed algorithm Contention-Aware Latency Minimal (CALM) is able to reduce unnecessary turns that would otherwise impose additional router pipeline latency to packets, as well as adjust forwarding traffic to reduce network contention latency. Simulation results show that the proposed algorithm can achieve, on average, 3.4X reduction in the number of turns, 24.8% reduction in contention latency, and 14.12% reduction in the overall packet latency.

A Classification and Evaluation Framework for NoC Mapping Strategies

Network on Chip (NoC) is a new communication medium used for systems-on-chip (SoCs). In an SoC, the placement of the communicating elements across the network has an impact on system performance. Such a placing is called the MAPPING phase in networks on chip design process. Many approaches dealing with the mapping phase have been proposed but selecting the best technique for a given NoC remains a challenging problem. This paper attempts to provide an answer to this issue. It motivates and presents a definition and a classification according to some criteria: (i) the algorithms used for solving the mapping problem, (ii) the moment in which the mapping is executed, (iii) the impact of combining mapping with other phases during NoC design and (iv) the target architecture.