Analytical Modeling of the SMART NoC

Abstract

With the increasing number of components in multiprocessor systems-on-chip, standard bus based communication architectures face a formidable scalability challenge. Network-on-chip (NoC), a type of communication architecture, addresses this scalability problem by distributing the communication resources among the communicating components. A huge bottleneck to modern NoC design is its extremely slow simulation/prototyping phase. Traditionally, analytical performance models have been used to speed up this phase. However, the currently available analytical models are not applicable to state-of-the-art NoCs. This forces NoC designers to rely on simulation/prototyping. In this work, we propose an analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers. Our method registers a prediction error in network latency that is as low as 1 percent, and on an average below 2.5 and 8.4 percent, respectively, compared with the cycle-accurate GARNET network simulator and the gem5 full-system simulator running the PARSEC benchmark suite. The method also leads to two orders of magnitude speedup in computation time. It can account for variations in NoC design parameters, such as the maximum number of hops per cycle, number of virtual channels, flit size, buffer depth per virtual channel, etc. Even when these NoC design parameters are varied, our method's results remain within 5 percent of GARNET's results.