Secure Routing Framework for Mitigating Time-Delay Trojan Attack in System-on-Chip

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In order to meet the complex requirements of the semiconductor market, the packet-based on-chip interconnect IP; Network-on-Chip (NoC) used in System-on-Chips (SoCs), provides provisions for in-house designers to customise the NoC design. This opens a backdoor for the adversary to insert malicious circuits to deploy attacks like exposing cryptography keys, resource depletion attacks, etc. A malicious implant, such as a Hardware Trojan (HT) on NoC that initiates a delay-of-service attack, can tamper with the system and the application performance. In this work, we model an HT that mounts a time-delay attack in a NoC by violating the path selection strategy used by the route compute unit of the adaptive NoC router. Our experimental analysis shows that the proposed HT increases the packet latency by 14.5% and degrades the system performance (IPC) by 15% over the Baseline. For HT detection, we propose a framework that uses packet traffic analysis and path monitoring to localise the HT. We also propose a security wrapper module for the route compute unit that suppresses the effect of HT with an average IPC reduction of only 1.8% over the Baseline.