Network on Chip and Its Low Power Techniques

Abstract

The advent of Network-On-Chip (NoC) architecture has significantly revolutionized the design of complex System-On-Chip (SoC) systems by providing scalable and efficient communication infrastructures. NoC architectures offer advantages such as high bandwidth; low latency and better scalability compared with traditional bus-based communication architectures. However, the ever-increasing demand for higher performance and lower power consumption poses significant challenges for NoC designers. This article reviews the basic architectures and design issues of NoCs with SoCs and further extended with research challenges and low power techniques. Key Words: Network-On-Chip, System-On-Chip, latency and scalability