Statistical traffic pattern for mixed torus topology and pathfinder based traffic and thermal aware routing protocol on NoC

Abstract

The network-on-chip (NoC) is an intra-communication on the chip extended from system-on-chip (SoC). The NoC design suffers from high failure rates due to the problem of routing in the traffic conditioning. In this paper, a realistic traffic pattern is used to verify the proposed routing scheme of the NoC with the novel design topology. Here a topology named mixed-torus topology is designed with the combination of processing block and the non-processing block that has the information about the processing block, which are associated with its torus block. The designed topology is presented with the encoder application model, and the set of tasks are mapped and scheduled to the processing block by the spider monkey optimization algorithm. Then the routing of data through the non-processing block is done by the pathfinder based traffic and thermal aware adaptive routing protocol (PFTTAR), which will perform the path diversity phase and the path selection phase for better routing. The designed NoC is then treated with the statistical traffic pattern generation for the analytical study of the proposed work and is implemented in Xilinx.