Negative Capacitance FET Research Articles

Compact modeling of short-channel effects in back-gated 2D negative capacitance (NC) FETs

The negative capacitance field-effect transistor with 2D channel material (2D NC-FET) holds significant promise for low-power applications owing to its remarkable resilience against short-channel effects (SCEs) and favorable noise characteristics. In this study, we establish a compact current–voltage (I–V) model for short-channel back-gated 2D NC-FETs with metal-ferroelectric-metal–insulator–semiconductor structure by self-consistently solving the two-dimensional Poisson, drift–diffusion and Landau–Khalatnikov equations. The proposed model is valid and continuous throughout the entire operating regime, including the fully-depleted region, partly-depleted region, and accumulation region. Furthermore, we derive analytical equations for the threshold voltage ( VTH ) and subthreshold swing ( SS ) of back-gated 2D NC-FETs based on the developed I–V model. Lastly, we elucidate the influence mechanisms of various device parameters and voltage bias on the subthreshold characteristics of short-channel back-gated 2D NC-FETs using the proposed I–V model in conjunction with analytical expressions of VTH and SS . Our findings reveal that back-gated 2D NC-FETs shows unconventional degradation behavior in VTH and SS, resulting from the competition between traditional SCEs and novel negative capacitance effects.

Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

Computing in-memory (CiM) is an alternative to von-Neumann architectures for energy efficient AI edge computing architectures with CMOS scaling. Approximate computing in-memory (ACiM) techniques have also been recently proposed to further increase the energy efficiency of such architectures. In the first part of the work, a negative capacitance FET (NCFET) based 6T-SRAM CiM accurate full adder has been proposed, designed and performance benchmarked with equivalent baseline 40 nm CMOS design. Due to the steep slope characteristics of NCFET, at an increased ferroelectric layer thickness, T fe of 3 nm, the energy consumption of the proposed accurate NCFET based CiM design is ∼82.48% lower in comparison to the conventional/Non CiM full adder design and ∼85.27% lower energy consumption in comparison to the equivalent baseline CMOS CiM accurate full adder design at V DD = 0.5 V. This work further proposes a reconfigurable computing in-memory NCFET 6T-SRAM full adder design (the design which can operate both in accurate and approximate modes of operation). NCFET 6T-SRAM reconfigurable full adder design in accurate mode has ∼4.19x lower energy consumption and ∼4.47x lower energy consumption in approximation mode when compared to the baseline 40 nm CMOS design at V DD = 0.5 V, making NCFET based approximate CiM adder designs preferable for energy efficient AI edge CiM based computing architectures for DNN processing.

Unveiling the reliability of negative capacitance FinFET with confrontation of different HfO2-ferroelectric dopants

The CMOS compatibility of Negative Capacitance (NC) FETs has been enhanced tremendously after introducing a thin film-doped HfO2 as a ferroelectric (FE) layer. For a given FE layer, the NC property is governed by specific HfO2 dopants (e.g., La, Zr, Al, Sr, Gd, Y, and Si). Thus, the TCAD simulation considerably depends on the dopant-specific Landau parameters (αx,βx,γx,ρx,gx), and its solidity needs proper attention. Further, the reliability of the NC devices is severely affected by process variations, i.e., interface trap charges, work function variation, random dopant fluctuation, and ambient temperature (external), which modulates the device threshold voltage (Vth); in turn, the device aging. In this paper, using well-calibrated TCAD models, we investigated reliability for the different dopant-specific NC-FinFET, in terms of Vth, ON current (ION), and OFF current (IOFF) modulation induced by: (i) the interface trap variability (ITV) considering the different trap concentration and energy location; (ii) the work function variability (WFV) considering different metal grain sizes (Gr); (iii) the random dopant fluctuations (RDF); and (iv) the ambient temperature. In this way, the device aging is calculated by inspecting Vth shift by ±50mV. These investigations pave the path for realizing a reliable NC-FinFET design.

A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis

This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in ION (ON-current), 73.58% in IOFF (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade, and a barrier rising of 52.38%. This is due to prior DC analysis that led to the extraction of the electrical parameters such as ION, IOFF, SS and threshold voltage (VT). After that, dimensional analysis is being done in terms of gate length (LG), fin widths (Wfin1 and Wfin2), and fin heights (Hfin1 and Hfin2). The optimized dimensions for this study are LG = 18 nm, Wfin1 = 5 nm, Wfin2 = 3 nm, Hfin1 = 50 nm, and Hfin2 = 14 nm. From this point on, using the same SNC-FinFET with the optimized dimension, varying the temperature from 250 K to 400 K, degrades the RF/analog characteristics while exhibiting the opposite trend for linearity, with improvements of 40.36%, 67.42%, 49.59%, and 62.31% in the 2nd order harmonic, 3rd order harmonic, 2nd order Voltage Intercept Point, and 3rd order Voltage Intercept Point, respectively. The proposed device performance is also analyzed at the circuit level followed by noise margin calculation where at T = 400 K 46.36% of improvement in noise margin is encountered.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Design and Optimization of Ferroelectric Spacer Engineered Modified Bi-Level Negative Capacitance FET: An Analog/RF Evaluation Perspective

Design and Optimization of Ferroelectric Spacer Engineered Modified Bi-Level Negative Capacitance FET: An Analog/RF Evaluation Perspective

Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature

This paper represents an in-depth investigation of low to high frequency noise performance of highly doped double pocket double gate NCFET (HDDP-DG-NCFET) and single gate NCFET (SG-NCFET) in the existence of Uniform and Gaussian trap charges at various frequencies and temperatures (200 K–400 K). The drain current noise spectral density (Sid) and Gate voltage noise spectral density (Svg) at different frequencies in existence of both type of trap charges are explored. In addition, the Sid as a function of frequency for various ferroelectric thicknesses (Tfe) is examined in the existence of Uniform trap charges. The findings show that, at lower frequencies flicker noise dominates, while at higher frequencies, the dominant noise element is diffusion noise. For the whole range of considered frequencies, the Generation-Recombination (G-R) noise is more substantial in existence of trap charges. It has been found that, the net Sid value of the HDDP-DG-NCFET for Uniform and Gaussian types of trap distribution is 6.98 × 10−14A2/Hz and 6.17 × 10−14A2/Hz, respectively. Moreover, the examination of Sid for various Tfe in presence of traps illustrates the significance of the ferroelectric layer in obtaining lower value of net Sid, particularly in the higher frequency region and the minimal net Sid value for Tfe = 7 nm as compared to other Tfe values. Finally, to examine the device's reliability, the temperature investigation for the noise in the non-existence and existence of trap charges demonstrates that, the impact of an increase in noise caused by the existence of trap charges is much pronounced at lower temperatures and smaller gate voltages, where G-R noise is observed to be the dominant noise component.

Performance optimization of high-K GAA-PZT negative capacitance FET MFIS silicon nanowire for low power RFIC and analog applications

In this article, Gate-All-Around Lead Zirconate Titanate Negative Capacitance (GAA PZT- NCFET) based Silicon Nanowire (SiNW) device architecture is investigated for the RF/Analog applications using Sentauras TCAD simulations. In this study the variation of ferroelectric layer thicknesses (tfe) has been systematically investigated. The proposed device yields higher values of on current, transconductance, cut off frequency, TFP, and Ion/Ioff ratio and lower values of off current, SS and threshold voltage, compared to baseline device. The proposed device delivers Ion, gm, fT, and TFP as 3.38 mA, 9.6 mS, 7.625 THz, and 74.85 THz V−1, respectively which are 220%, 219%, 95% and 259% respectively, higher than the baseline device. Moreover, the Ion/Ioff ratio for the proposed work is 8 × 1013 which is 7.1 × 103 times that of baseline device showing a monumental increment in this ratio. Furthermore, the effect of FE thicknesses on various linearity parameters, higher order harmonics, voltage intercept points (VIP2, VIP3), third order power intercept (IIP3) and third order intermodulation distortion (IMD3) have been investigated thoroughly. The proposed device structure offers lower values of higher order harmonics and higher values of voltage intercept points. Also, the IIP3 and IMD3 have been improved. Therefore, the linearity parameters of the device have been significantly improved when compared to the baseline device. The alluring results have been utilized to optimize the bias point of the presented device. Owing to the improved RF/Analog and linearity performance, the presented device could be utilized for imminent next generation low power RFIC applications.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Comparative Analysis of Noise Behavior of Highly Doped Double Pocket Double-Gate and Single-Gate Negative Capacitance FET

Comparative Analysis of Noise Behavior of Highly Doped Double Pocket Double-Gate and Single-Gate Negative Capacitance FET

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

An Energy-Efficient Computing-in-Memory (CiM) cell design utilizing a Negative Capacitance (NC) FET has been proposed to support computing architectures for Deep Neural Networks (DNNs). The NCFET device characteristics for CiM architectures have been studied to determine an optimal device performance window by changing the thickness of ferroelectric layer (Tfe). The performance metrics such as read margin (RM), write margin (WM), read energy and write energy of NCFET 6 T SRAM cell are analyzed with varying Tfe at two different supply voltages 0.3 V and 0.5 V respectively. NCFET based SRAM cell design achieves higher RM and WM at Tfe of 3 nm and lower energy consumption at 1 nm Tfe as compared with the baseline SRAM cell design at both VDD = 0.3 V and VDD = 0.5 V respectively. 6 T NCFET based CiM cell design for performing basic input-weight product operation (IWP) has been demonstrated and performance comparison is done with baseline CMOS design at VDD = 0.3 V and VDD = 0.5 V. In comparison with the baseline CMOS CiM cell design, NCFET based SRAM CiM design achieves ∼2.59x and 1.62x lower energy consumption at VDD = 0.3 V and VDD = 0.5 V respectively with an optimal Tfe window of 1–3 nm.

Impact of interface trap charges on analog/RF and linearity performances of PGP negative capacitance FET

Here, we examine the impact of various trap charges on the baseline and NC PGPFET (negative capacitance partial ground plane FET) by applying localized charges (donor/acceptor) at the semiconductor/insulator interface. Examining different parameters has revealed that donor traps enhance device characteristics while acceptor traps reduce device performance. Therefore NC effect is generated by introducing a ferroelectric material in the gate stack that enhances the device performance by the voltage amplification process. Doped HfO2 is taken as the ferroelectric material because of its high dielectric capacitance and reliable polarization rate. Along with DC, RF/Analog factors such as trans-conductance (gm), output conductance (gds), trans-conductance generation factor (TGF), cut-off frequency (ft), trans-conductance frequency product (TFP) have been examined for the potential use of NCFET for RF applications. Additionally, linearity parameters like gm2, gm3, VIP2, VIP3 and intermodulation distortion (IMD3) is also compared for both traps. Due to its improved performance, NC PGPFET is appropriate for low-voltage analog/RF applications.

Exploration of temperature stability of linearity and RF performance metrics for PGP negative capacitance FET

The present work focuses on investigating the performance of partial ground plane selective buried oxide negative capacitance (NC) field-effect transistor (NCFET) electrical properties at high temperatures. The performance of the device has been studied between the temperature of 300–400 K using the Landau–Khalatnikov equation with the Poisson’s equation. In NCFET, ferroelectric material in the gate stack generates NC effect that enhances the device performance by the voltage amplification process. Doped is used as the ferroelectric material because of its high dielectric capacitance and reliable polarization rate. This work primarily focuses on examining the effects of temperature change on the device’s dc performance metrics, analog/radio frequency performance parameters, and linearity performance parameters. Compared to kT/q, sub-threshold slope rises more rapidly as temperature rises and diminishing the ferroelectric effect after 350 K. Also reduced intrinsic delay at higher temperatures make the device an great option for ultra-low-power and high switching speed applications. Additionally, the proposed device performs better in terms of linearity at greater temperatures.

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

Energy-efficient and secure cipher design for resource constrained IoT applications is a pressing challenge with CMOS technology scaling and increased hardware attacks. This work presents the potential and design challenges exploring Negative Capacitance FETs (NCFETs) for energy efficient and differential power analysis (DPA) attack resilient circuit/cipher design at scaled supply voltages. Design and performance benchmarking of one such ultra-light weight block cipher, i.e. PRESENT-80 exploring 40 nm NCFET device technology is demonstrated and evaluated resiliency against DPA attack for the first time. 40 nm NCFETs show optimum device performance with a ferroelectric layer thickness (tfe) in the range of 3 nm–5 nm. NCFET with tfe of 5 nm shows ∼15.7 × higher ON current, 1.77 lower leakage current and subthreshold swing of 49mV/dec compared to the baseline CMOS device. NCFET based PRESENT-80 block cipher design achieves ∼3.2 × lower energy consumption compared to the baseline equivalent 40 nm CMOS design under similar design constraints. NCFET PRESENT-80 cipher design is evaluated against DPA attack and results indicate NCFET based cipher design to be highly resilient compared to the baseline CMOS design. With the non-linearity in power traces caused by the additional capacitance of NCFET device structure, the proposed NCFET PRESENT cipher design achieves ∼4 × increased attacker effort ratio and low Signal-to-noise ratio (SNR) values compared to the equivalent baseline CMOS design.

Negative capacitance field-effect transistor with hetero-dielectric structure for suppression of reverse drain induced barrier lowering

Recently, negative capacitance FETs (NCFET) using ferroelectric materials as a gate oxide have received much attention as one of the candidates for next-generation low power/high-performance devices because they can have sub-60 mV/dec subthreshold swing at room temperature through the channel potential amplification. However, the reverse drain induced barrier lowering phenomenon occurs by the local rising of the drain-side conduction energy band when a high drain voltage is applied to NCFETs, leading to the degradation of on-current and subthreshold swing. In this work, a novel NCFET with hetero-dielectric (HD-NCFET), where the gate dielectric consists of source-side ferroelectric material and drain-side paraelectric silicon dioxide (SiO2), is proposed to prevent the undesirable reverse drain induced barrier lowering phenomenon. Through technology computer-aided design simulations, the effects of operating voltage and SiO2 length on the electrical characteristics of the HD-NCFET are rigorously analyzed to optimize and maximize its device performance.

Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants

Attaining the ferroelectric (FE) polarization in a thin HfO2 layer using a specific dopant is a widely adopted way to realize Negative Capacitance (NC) FET. In a general TCAD simulation study of NC-based devices, the NC property of the FE layer is strongly dependent on the values of Landau parameters (α,β,γ,ρ,g), which are unique for specific dopants and FE thickness. In this paper, for the first time, we investigated the reliability of TCAD simulations with which NC FinFET is simulated for a specific dopants-based FE-HfO2 layer. The possible dopants used to realize a thin-HfO2 layer as a FE layer are Al, Gd, La, Si, Sr, Y, and Zr. Each dopant has different (α,β,γ,ρ,g) and thus offers a different NC regime of operation, i.e., S-curve. α and β are the dominant parameters if we consider the uniform polarization under quasi-static analysis. Further, the change in ambient temperature alters the value of α, resulting in changes in the NC-state. Hence, for the reliable TCAD-based NC study, the precise selection of Landau parameters and dopants is needed for optimized performances.

Investigation on performance degradation due to induced interface trapped charges on HSO based FDSOI NCFET and sustaining it through back-gate bias

In this article, a variant of doped HfO2 based ferroelectric capacitor i.e. silicon doped HfO2 (hafnia-silica/HSO) is investigated for analytical feasibility and viability for negative capacitance FET (NCFET) applications. Investigations are carried out extensively using well calibrated and validated numerical simulations to find out the optimum ferroelectric thickness (tf) of HSO thin-film for the NCFET to operate in hysteresis-free regime. The optimized NCFET is then subjected to the variation of back-gate bias (V ) to exploit threshold-voltage () shift phenomena might further improve NCFET performance. In continuance, the optimized NCFET has been introduced with interface trap (+Nit) charges at the oxide–semiconductor interface to emphasize on the reliability deflation caused at process level design. Hence, this has allowed us to concisely observe and analyse performance degradation aspect of the NCFET with numerical simulations. Also, a feasibility to recuperate the degraded performance caused by +Nit with utilizing −V is carried out. The performance metrics used in the numerical simulation for the evaluation of HSO ferroelectric NCFET are: sub-threshold slope, charge variation with gate-voltage and ferro voltage, surface potential, , drain-current and amplification factor.

Impact of unpreventable induced interface trapped charges on HZO based FDSOI NCFET

In this paper, the effect of oxide-semiconductor interface trapped charges on the performance of 22-nm Fully Depleted Silicon on Insulator (FDSOI) Negative Capacitance FET (NCFET) has been systematically investigated. Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) type NCFET with zirconium doped HfO2 (HZO) as the ferroelectric material is considered for this work. The simulation of the underlying Metal-Insulator-Semiconductor (MIS) structure has been carried out in a well-calibrated TCAD environment to extract the gate charge. Which is subsequently used to solve 1D Landau-Khalatnikov (1D-LK) model to find the voltage across ferroelectric capacitor. The presence of trap charges is unavoidable in modern devices, which affects the charge balance equation as well as the performance & reliability of the device. NCFET being one of the potential candidates to be adopted by industry for ultra-low power applications in the future according to the International Roadmap for Devices and Systems (IRDS), investigation of trap charges becomes crucial. Due to its multilayer stacking, the transfer characteristics are analyzed for various ferroelectric thicknesses with exhibition of an intersection point, which is demonstrated for the first time. Simulation of variation of device performance metrics like minimum sub-threshold swing (min. SS), transconductance (gm), off-state drain current (Ioff) & amplification factor (AV) are analyzed and compared for various interface trapped charge densities. It is predicted that the device performance either enhances or degrade depending on the type of trapped charges present.

Physical investigation of subthreshold swing degradation behavior in negative capacitance FET

Physical investigation of subthreshold swing degradation behavior in negative capacitance FET

Performance of Broken Gap MoO3/ZnS Heterojunctions as Abrupt Electronic Switches, MOSFETs, Negative Capacitance FETs and Bandpass Filters Suitable for 3G/4G Technologies

Performance of Broken Gap MoO3/ZnS Heterojunctions as Abrupt Electronic Switches, MOSFETs, Negative Capacitance FETs and Bandpass Filters Suitable for 3G/4G Technologies