Negative capacitance field-effect transistor with hetero-dielectric structure for suppression of reverse drain induced barrier lowering

Abstract

Recently, negative capacitance FETs (NCFET) using ferroelectric materials as a gate oxide have received much attention as one of the candidates for next-generation low power/high-performance devices because they can have sub-60 mV/dec subthreshold swing at room temperature through the channel potential amplification. However, the reverse drain induced barrier lowering phenomenon occurs by the local rising of the drain-side conduction energy band when a high drain voltage is applied to NCFETs, leading to the degradation of on-current and subthreshold swing. In this work, a novel NCFET with hetero-dielectric (HD-NCFET), where the gate dielectric consists of source-side ferroelectric material and drain-side paraelectric silicon dioxide (SiO2), is proposed to prevent the undesirable reverse drain induced barrier lowering phenomenon. Through technology computer-aided design simulations, the effects of operating voltage and SiO2 length on the electrical characteristics of the HD-NCFET are rigorously analyzed to optimize and maximize its device performance.