Negative Bias Temperature Stress Research Articles

Electrical Characterization of Charge Polarity in AlF₃ Anti-Reflection Layers for Complementary Metal Oxide Semiconductor Image Sensors.

In this study, the charge polarity of aluminum fluoride (AlF3) as a function of varying thickness (tAlF3 = 20, 35, 50, 65, and 80 nm) was discussed. AlF3 films were deposited onto p-Si wafers via electron beam sputtering. Thickness dependent charge polarity and reliability issues under bias-temperature stress conditions were identified using a capacitance-voltage (C-V) characterization method. AlF3 was found to possess negative fixed charges, leading to a C-V curve shift toward the positive gate bias direction as tAlF3 was increased up to 50 nm. On the contrary, the C-V characteristics were dominantly affected by the positive charges of mobile ions and/or fluorine vacancies when tAlF3 was increased to more than 50 nm. Additionally, negative bias temperature stress (1 MV/cm, 473 K for 10 mins) increased insulator trapped charges and decreased interface traps in 20 nm thick AlF3 films. These results could be attributed to positively charged fluorine vacancies introduced by broken Al-F bonds within AlF3 films and the passivation of Si dangling bonds due to broken fluorine ions at the interface, respectively. It was believed that 20 nm thick AlF3 films sufficiently attracted holes from the Si substrate, forming a hole accumulation layer on the surface due to total charge polarity of the AlF3 dielectric being entirely governed by negative fixed charges as the thickness of AlF3 decreased. Based on these results, AlF3 films are proposed for use as an anti-reflection layer to replace HfO2 in CMOS image sensors.

Investigation of degradation mechanisms in low-voltage p-channel power MOSFETs under High Temperature Gate Bias stress

In this work we investigate the degradation mechanisms occurring in a p-channel trench-gate power MOSFET under High Temperature Gate Bias (HTGB) stress. The impact of negative bias temperature stress is analysed by evaluating relevant figures of merit for the considered device: threshold voltage, transconductance and on-resistance. Temperatures and gate voltages as large as 175 °C and −24 V, respectively, are adopted to accelerate the degradation in the device. Moreover, in order to investigate the origin of degradation mechanisms we analyse the interface states generation and the charge trapping processes, the impact of a switching gate voltage during the stress phase and the recovery phase after HTGB stress.

Stability improvements of InGaZnO thin-film transistors on polyimide substrates with Al2O3 buffer layer

We investigate the effects of atomic layer deposition (ALD)-grown Al2O3 buffer layer on the device characteristics of flexible amorphous InGaZnO thin-film transistors (TFTs) fabricated on ultrathin polyimide (PI) films. The TFT with a buffer layer exhibited a saturation mobility of 8.6 cm2 V−1 s−1 and a subthreshold swing of 0.16 V dec−1 after annealing at 150 °C. Under negative bias temperature stress at 40 °C, the turn-on voltage instabilities of TFTs with and without the buffer layer were estimated to be −1.0 and −13.2 V, respectively. This marked difference is mainly due to the adsorption of water molecules on the PI film resulting in a positively charged surface.

Atomic Layer Deposited ZrxAl1−xOy Film as High κ Gate Insulator for High Performance ZnSnO Thin Film Transistor

In this work, the high κ ZrxAl1−xOy films with a different Zr concentration have been deposited by atomic layer deposition, and the effect of Zr concentrations on the structure, chemical composition, surface morphology and dielectric properties of ZrxAl1−xOy films is analyzed by Atomic force microscopy, X-ray diffraction, X-ray photoelectron spectroscopy and capacitance-frequency measurement. The effect of Zr concentrations of ZrxAl1-xOy gate insulator on the electrical property and stability under negative bias illumination stress (NBIS) or temperature stress (TS) of ZnSnO (ZTO) TFTs is firstly investigated. Under NBIS and TS, the much better stability of ZTO TFTs with ZrxAl1−xOy film as a gate insulator is due to the suppression of oxygen vacancy in ZTO channel layer and the decreased trap states originating from the Zr atom permeation at the ZTO/ZrxAl1−xOy interface. It provides a new strategy to fabricate the low consumption and high stability ZTO TFTs for application.

Semiconductor behavior of Li doped ZnSnO thin film grown by mist-CVD and the associated device property

Lithium (Li)-doped zinc tin oxide (ZTO) films were successfully grown by mist chemical vapor deposition (mist-CVD) under ambient atmosphere at a relatively low process temperature (∼350 °C). The effects of Li incorporation on the chemical and physical properties of the host ZTO semiconductor were studied, along with the electrical characteristics of the associated thin film transistors (TFTs). The devices incorporating Li-ZTO active layers grown with a 1 mol % Li precursor exhibit superior electrical performance, with representative saturation mobility of 24.7 cm2/V and on/off ratio of ∼1010, compared to pure ZTO TFTs (exhibiting a mobility of 14.6 cm2/V and on/off ratio of ∼108). Under negative bias temperature stress (NBTS), the Li-ZTO TFTs undergo relatively small threshold voltage shifts (ΔVth) of approximately −0.42 V, while the undoped ZTO TFTs exhibit net ΔVth values near −3.21 V. Here it is suspected that Li ions enhance the device performance by contributing additional free carriers, while passivating the defects that act as carrier traps. Li doping is thus an effective way to improve both the charge transport properties and stability of ZTO semiconductor devices, which may be realized by means of a cost-effective mist-CVD process.

Enhanced stability of thin film transistors with double-stacked amorphous IWO/IWO:N channel layer

In this work, bottom-gate top-contact thin film transistors with double-stacked amorphous IWO/IWO:N channel layer were fabricated. Herein, amorphous IWO and N-doped IWO were deposited as front and back channel layers, respectively, by radio-frequency magnetron sputtering. The electrical characteristics of the bi-layer-channel thin film transistors (TFTs) were examined and compared with those of single-layer-channel (i.e., amorphous IWO or IWO:N) TFTs. It was demonstrated to exhibit a high mobility of 27.2 cm2 V−1 s−1 and an on/off current ratio of 107. Compared to the single peers, bi-layer a-IWO/IWO:N TFTs showed smaller hysteresis and higher stability under negative bias stress and negative bias temperature stress. The enhanced performance could be attributed to its unique double-stacked channel configuration, which successfully combined the merits of the TFTs with IWO and IWO:N channels. The underlying IWO thin film provided percolation paths for electron transport, meanwhile, the top IWO:N layer reduced the bulk trap densities. In addition, the IWO channel/gate insulator interface had reduced defects, and IWO:N back channel surface was insensitive to the ambient atmosphere. Overall, the proposed bi-layer a-IWO/IWO:N TFTs show potential for practical applications due to its possibly long-term serviceability.

Effect of Hydrogen on Reliability with Various Deposition Temperatures of Al2O3 Gate Insulator in In-Ga-Zn-O Thin Film Transistors

To achieve the next generation displays, it is becoming increasingly important to develop backplane technology with superior characteristics such as high mobility, high stability, and high transparency. Among the several candidates for suitable backplane in high definition display, amorphous In-Ga-Zn-O (a-IGZO) oxide semiconductor TFTs have attracted much interest due to its high mobility, optical transparency, and large area uniformity. However, due to the intrinsic problem of a-IGZO TFTs caused by oxygen vacancy and hydrogen, it is hard to control of threshold voltage (Vth) and stability under various stress conditions. One of them, hydrogen is the main factor closely related to reliability. According to previous studies, hydrogen acts as positive roles by defect passivation and also play negative roles in creating new defects in a-IGZO active layer. However, incorporation and diffusion of hydrogen into the active layer is an unavoidable issue during the TFTs fabrication, and it is important to control it so that hydrogen plays a positive role. So, in this study, we conducted experiments to verify the effect of hydrogen on the reliability by modifying the Al2O3 gate insulator layer (GI) deposition process using atomic layer deposition (ALD) method. In order to verify the relationship between the hydrogen and electrical properties of a-IGZO TFTs, we fabricated top gate bottom contact (TGBC) structures and applied different GI deposition temperature (Tdep) for controlling the amount of hydrogen. [1] Al2O3 GI deposited using trimethylaluminum (TMA) and H2O precursor. Each Tdep are 200, 250, 270 and 300 degree, respectively. As a result of Al2O3 single thin film analysis using secondary ion mass spectroscopy (SIMS) method, it was confirmed that the Al2O3 thin film deposited at high Tdep has a relatively small amount of hydrogen than the Al2O3 thin film deposited at low Tdep. And then, TFT devices a, b, c, and d were fabricated using Al2O3 GI with different Tdep of 200, 250, 270 and 300 degrees, respectively. As a result, there was no significant difference between the devices. All devices had subthreshold swing (SS), value of 0.178 ~ 0.225 V, turn on voltage (Von) of -0.16 ~ -0.44V, hysteresis of 0.13 ~ 0.27 V and field effect mobility (μFE) of 9.6 ~ 10.55 cm2/Vs. This trend was similar to positive bias temperature stress (PBTS) and negative bias temperature stress (NBTS) reliability. However, the reliability of negative bias illumination stress (NBIS) was significantly different for each device. Under the NBIS condition, the Vth shift of each TFT was -4.36 V for a TFT, -4.36 V for b TFT, -3.72V for c TFT, -2.48 V for d TFT. These results indicate that the NBIS characteristic is improved as the Tdep of Al2O3 GI increases and proves that reliability varies with the amount of hydrogen. This suggests that as hydrogen increases, more hydrogen-induced defects are formed at the interface between GI and a-IGZO active layer, which causes trapping of positive charges. This phenomenon can be explained by non-bridging oxygen hole center (NBOHC) method, which is one of the positive charge trapping models, and the mechanism for the role of hydrogen in the a-IGZO TFTs can be identified. [2] Base on these experimental results, we will propose the way to optimize condition of GI deposition process for high stability and high performance in a-IGZO TFTs. [1] S.J. Yun, K.-H. Lee, J. Skarp, H.-R. Kim and K.-S. Nam, J. Vac. Sci. Technol. A, 15(6) (1997) [2] M. Tsubuku, R. Watanabe, N. Ishihara, H. Kishida, M. Takahashi, S. Yamazaki, Y. Kanzaki, H. Matsukizono, S. Mori, T. Matsue, SID 2013 DIGEST. 169 (2013)

P-6.6: Fabrication of Cu BCE-structure IGZO TFTs for 85-inch 8K4K 120Hz GOA LCD Display

The electrical characteristics of the back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs) were studied. The passivation layer ,the selection of color filter material and design of GOA TFT structure were modified for lessening the influence of H2O molecules adsorbing on the back channel of the BCE-structure. The negative and positive bias temperature stress results revealed that the optimized GOA TFTs exhibited good device reliability. Finally, a high performance 85-inch 8K4K 120Hz GOA LCD was demonstrated.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Photoluminescence Study of Amorphous InGaZnO Thin-Film Transistors

The defects within optical gap of the amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) before and after bias temperature stress (BTS) are studied using in situ photoluminescence (PL) spectroscopy. After applying positive BTS, the TFT threshold voltage (Vth) increased, and intensity of deep-level PL emission peak at 1.82 eV became stronger. The exact opposite is observed when negative BTS is applied. Both the 250-nm bulk a-IGZO film and 50-nm channel region TFT show the same PL peak locations of 3.35 and 1.82 eV. From the measured results and density of state model of a-IGZO, the radiative recombination between electrons trapped in oxygen-related acceptor-like states and holes in the valence band is responsible for the deep-level PL emission. This method of measuring the PL response within the TFT channel region could be used as a tool to evaluate the quality of a-IGZO TFT manufacturing processes.

Effect of Annealing Temperature on Enhancement of Electrical Performance and Stability of Amorphous SiZnSnO Thin Film Transistors

Amorphous Si doped ZnSnO (a-SZTO) was used to investigate the effect of annealing temperature on variation of the electrical performance and stability of amorphous oxide semiconductors used in thin film transistors. It was observed that by as increasing the annealing temperature, the electrical characteristics such as field-effect mobility (μFE), subthreshold swing, and on-to-off current ratio (Ion/off) were enhanced because while the carrier concentration increased the defect decreased. The devices were annealed at 400, 500, and 600 °C. Transfer curves were obtained at 400 and 500 °C, but at 600 °C, a conductive characteristic were revealed because of increased carrier concentration. The negative bias temperature stress (NBTS) was measured at 600 °C. A gate voltage was applied to the devices − 20 V for 2 h. Threshold voltage shift (ΔVth) was measured to be about 5.6 and 1.59 V at 400 and 500 °C respectively. This enhancement was mainly due in the decrease in defects by annealing. By increasing the annealing temperature, the defect density decreased and stability was enhanced. Transmission line method was used to find the relation between the electrical characteristics and the annealing temperature. The total resistance decreased as the annealing temperature was increased, and showed very good agreement with the results of NBTS. In conclusion, the a-SZTO TFT showed the highest electrical performance as well as excellent stability at the annealing temperature of 500 °C.

Influence of Channel Layer Thickness on the Instability of Amorphous SiZnSnO Thin Film Transistors Under Negative Bias Temperature Stress

In this study, amorphous silicon‐zinc‐tin‐oxide thin film transistors (a‐SZTO TFTs) are fabricated by radio‐frequency magnetron sputtering at room temperature, and the influence of various channel thicknesses on their electrical performance and stability is reported. Under the negative bias temperature stress, the transfer curve exhibits threshold voltage shift in the negative direction and degradation of subthreshold swing. In addition, the hump effect occurs in the thick channel, which is primarily due to an increase in total trap density from 5.0 × 1011 to 3.5 × 1012 cm−2 with an increase in the channel layer thickness from 12 to 72 nm. These results agree well with the increase in the bulk trap density because all a‐SZTO TFTs have the same interface; therefore, the interface trap density is excluded. Thicker SZTO TFTs show the hump effect, as they have more donor‐like states in the shallow level. Furthermore, temperature stress at 300–333 K and the activation energy (Ea) falling rate are calculated for a‐SZTO TFTs. The Ea falling rate decreases from 0.103 to 0.010 eV V−1 with increasing channel thickness. Consequently, an a‐SZTO TFT with a 12‐nm channel layer thickness shows a large Ea falling rate (0.103 eV V−1) and a small threshold voltage shift of 4.74 V without the hump effect and degraded electrical performance.

Abnormal Bias-Temperature Stress and Thermal Instability of $\beta$ -Ga2O3 Nanomembrane Field-Effect Transistor

In this paper, we report on the electrical and thermal instability of $\beta $ -Ga2O3 nanomembrane field-effect transistor with a bottom-gate configuration. The fabricated device exhibits high electrical performance of field-effect mobility of up to 60.9 cm2/ $\text{V}\cdot \text{s}$ , on/off-current ratio of 109, and subthreshold slope of 210 mV/dec. However, we observe abnormal positive threshold voltage ( ${V} _{\mathrm{ TH}}$ ) shifts under negative bias-temperature stress at an elevated operating temperature of 80 °C as well as under temperature-dependent transfer characteristics up to 200 °C. This abnormal instability is significantly influenced by the surface depletion effect, and is discussed using energy band diagram. The opposite ${V} _{\mathrm{ TH}}$ shift was achieved by applying atomic-layer deposited Al2O3 passivation layer.

高可靠性Cu BCE a-IGZO TFTs的制作

Back channel etched (BCE) amorphous InGaZnO (a-IGZO) can be fabricated with fewer photolithography masks and achieve smaller parasitic capacitance. However, the back channel of the BCE a-IGZO TFT is vulnerable to acid and plasma damage, which leads to problems of TFT uniformity and stability. In particular, with the introduction of gate driver on array (GOA) technology, it is increasingly urgent to improve the electrical uniformity and stability of TFTs. Therefore, it is an urgent requirement for technology and market to develop high reliability BCE IGZO TFTs. The electrical characteristic of the BCE configuration based a-IGZO TFTs were studied. The passivation layer, the selection of color filter material and design of GOA TFT structure were modified for lessening the influence of H2O molecules adsorbing on the back channel of the BCE-structure. The negative and positive bias temperature stress(N/PBTS) results revealed that the optimized GOA TFTs exhibited good device reliability-the Vth shift under gate voltage of -30 V at 80℃ is less than 1 V for 2 000 s. Finally, a high performance 215.9 mm(85 in) 8K4K 120 Hz GOA LCD was demonstrated.

Extraction method of interfacial injected charges for SiC power MOSFETs

An improved novel extraction method which can characterize the injected charges along the gate oxide interface for silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed. According to the different interface situations of the channel region and the junction FET (JFET) region, the gate capacitance versus gate voltage (Cg-Vg) curve of the device can be divided into three relatively independent parts, through which the locations and the types of the charges injected in to the oxide above the interface can be distinguished. Moreover, the densities of these charges can also be calculated by the amplitudes of the shifts in the Cg-Vg curve. The correctness of this method is proved by TCAD simulations. Moreover, experiments on devices stressed by unclamped-inductive-switching (UIS) stress and negative bias temperature stress (NBTS) are performed to verify the validity of this method.

The self-activated radical doping effects on the catalyzed surface of amorphous metal oxide films

In this study, we propose a self-activated radical doping (SRD) method on the catalyzed surface of amorphous oxide film that can improve both the electrical characteristics and the stability of amorphous oxide films through oxidizing oxygen vacancy using hydroxyl radical which is a strong oxidizer. This SRD method, which uses UV irradiation and thermal hydrogen peroxide solution treatment, effectively decreased the amount of oxygen vacancies and facilitated self-passivation and doping effect by radical reaction with photo-activated oxygen defects. As a result, the SRD-treated amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) showed superior electrical performances compared with non-treated a-IGZO TFTs. The mobility increased from 9.1 to 17.5 cm2/Vs, on-off ratio increased from 8.9 × 107 to 7.96 × 109, and the threshold voltage shift of negative bias-illumination stress for 3600 secs under 5700 lux of white LED and negative bias-temperature stress at 50 °C decreased from 9.6 V to 4.6 V and from 2.4 V to 0.4 V, respectively.

Investigating degradation behaviors induced by mobile Cu ions under high temperature negative bias stress in a-InGaZnO thin film transistors

This letter investigates the effect of negative bias temperature stress (NBTS) on amorphous InGaZnO4 thin film transistors with copper electrodes. After 2000 s of NBTS, an abnormal subthreshold swing and on-current (Ion) degradation is observed. The recovery of the Id-Vg curve after either annealing or positive bias temperature stress suggests that there are some native mobile copper ions in the active layer. Both the existence of copper and the degradation mechanism can be confirmed by AC stress with different frequencies and by transmission electron microscope energy-dispersive X-ray spectroscopy analysis.

Degradation process by effect of water molecules during negative bias temperature stress in amorphous-InGaZnO thin-film transistor

We explained how H2O degrades amorphous-InGaZnO thin-film transistors. H2O caused serious degradation only during negative bias temperature stress (NBTS). Degradation was caused by molecules that were absorbed or diffused from the outside. We suggest that degradation under NBTS is caused by the migration of hydrogen ions among oxygen vacancies. Under illumination, the soaking time tS did not affect the threshold voltage shift ΔVth. We consider that this independence occurred because illumination caused ionization from the oxygen vacancy VO state to VO2+, which impeded hydrogen migration induced by electric field and thereby protected the device from degradation after exposure to water.

Bias stress instability of double-gate a-IGZO TFTs on polyimide substrate

In this study, flexible double-gate thin-film transistor (TFT)-based amorphous indium-galliumzinc- oxide (a-IGZO) was fabricated on a polyimide substrate. Double-gate operation with connected front and back gates was compared with a single-gate operation. As a result, the double-gate a- IGZO TFT exhibited enhanced electrical characteristics as well as improved long-term reliability. Under positive- and negative-bias temperature stress, the threshold voltage shift of the double-gate operation was much smaller than that of the single-gate operation.

P‐137: Vt Behaviors of LTPS‐TFT Fabricated on PI substrate for Flexible Applications

In this paper, one of goals is to elucidate Vt behaviors of a top gate LTPS‐TFT fabricated on the PI substrate exposed to the negative bias temperature stress (NBTS), hot carrier injection (HCI) and breakdown voltage (BV). Physical and device characterization intend to comprehend the structural dependency of LTPS‐TFT on Vt stability and reliability in comparison to the glass substrate. It is found that turn‐over Vt behaviors of a top gate LTPS‐TFT on the polyimide (PI) substrate depends on negative bias temperature stress (NBTS) conditions. Vt behaviors are attributed to LTPS‐TFT structure dependent intrinsic negative charges at the interface between the barrier and PI substrate, causing the accumulation of positive charges at the poly‐Si back channel. In fact, intrinsic process parameters, such as barrier thickness and PI cure conditions, play important roles to control interfacial charges at the interface. Finally, streamlined barrier process enables LTPS‐TFT on PI substrate to expand advanced flexible applications without compromising luminescence and reliability.