Effect of Annealing Temperature on Enhancement of Electrical Performance and Stability of Amorphous SiZnSnO Thin Film Transistors

Abstract

Amorphous Si doped ZnSnO (a-SZTO) was used to investigate the effect of annealing temperature on variation of the electrical performance and stability of amorphous oxide semiconductors used in thin film transistors. It was observed that by as increasing the annealing temperature, the electrical characteristics such as field-effect mobility (μFE), subthreshold swing, and on-to-off current ratio (Ion/off) were enhanced because while the carrier concentration increased the defect decreased. The devices were annealed at 400, 500, and 600 °C. Transfer curves were obtained at 400 and 500 °C, but at 600 °C, a conductive characteristic were revealed because of increased carrier concentration. The negative bias temperature stress (NBTS) was measured at 600 °C. A gate voltage was applied to the devices − 20 V for 2 h. Threshold voltage shift (ΔVth) was measured to be about 5.6 and 1.59 V at 400 and 500 °C respectively. This enhancement was mainly due in the decrease in defects by annealing. By increasing the annealing temperature, the defect density decreased and stability was enhanced. Transmission line method was used to find the relation between the electrical characteristics and the annealing temperature. The total resistance decreased as the annealing temperature was increased, and showed very good agreement with the results of NBTS. In conclusion, the a-SZTO TFT showed the highest electrical performance as well as excellent stability at the annealing temperature of 500 °C.