Influence of Channel Layer Thickness on the Instability of Amorphous SiZnSnO Thin Film Transistors Under Negative Bias Temperature Stress

Abstract

In this study, amorphous silicon‐zinc‐tin‐oxide thin film transistors (a‐SZTO TFTs) are fabricated by radio‐frequency magnetron sputtering at room temperature, and the influence of various channel thicknesses on their electrical performance and stability is reported. Under the negative bias temperature stress, the transfer curve exhibits threshold voltage shift in the negative direction and degradation of subthreshold swing. In addition, the hump effect occurs in the thick channel, which is primarily due to an increase in total trap density from 5.0 × 1011 to 3.5 × 1012 cm−2 with an increase in the channel layer thickness from 12 to 72 nm. These results agree well with the increase in the bulk trap density because all a‐SZTO TFTs have the same interface; therefore, the interface trap density is excluded. Thicker SZTO TFTs show the hump effect, as they have more donor‐like states in the shallow level. Furthermore, temperature stress at 300–333 K and the activation energy (Ea) falling rate are calculated for a‐SZTO TFTs. The Ea falling rate decreases from 0.103 to 0.010 eV V−1 with increasing channel thickness. Consequently, an a‐SZTO TFT with a 12‐nm channel layer thickness shows a large Ea falling rate (0.103 eV V−1) and a small threshold voltage shift of 4.74 V without the hump effect and degraded electrical performance.