Negative Bias Temperature Instability Reliability Research Articles

Impact of Channel Thickness on the NBTI Behaviors in the Ge-OI pMOSFETs With Al2O3/GeOx Gate Stacks

The impact of channel thickness on the negative-bias temperature instability (NBTI) behaviors has been studied for the Germanium-on-Insulator (Ge-OI) pMOSFETs. It is found that the permanent and recoverable defects are generated simultaneously during the NBTI stress of Ge-OI pMOSFETs. The lower NBTI is confirmed for the Ge-OI pMOSFETs with a thinner channel, due to the reduction of the band bending of Ev under a fixed electrical field of NBTI stress. Thus, the channel thickness scaling could be an effective method to improve the NBTI reliability for Ge-OI pMOSFETs.

NBTI Mitigation by Optimized HKMG Thermal Processing in a FinFET Technology

It has become more challenging to suppress the negative bias temperature instability (NBTI) in advanced FinFET technology which is largely originated from the dielectric/channel interface in HKMG structure. In this work, we report the experimental approach to mitigate the NBTI in 14-nm FinFET devices through HKMG thermal processing optimization. The NBTI reliability degradation arises from the formation of defective SiO₂ interlayer and the interface traps based on a quantitative analysis. Using optimized post-dielectric annealing (PDA) and post-Si-cap annealing (PCA) processing, an improved balance between the SiO₂ interlayer quality and high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula>/SiO₂ interface trap density has been achieved. The NBTI <inline-formula> <tex-math notation="LaTeX">${V}_{t}$ </tex-math></inline-formula> shift and device local variation are effectively suppressed. This provides an instructive pathway to enhance the NBTI reliability in FinFET through process optimization approaches.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation.In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2.Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density.

NBTI and HCI Aging Prediction and Reliability Screening During Production Test

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.

A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing

Neuromorphic hardware with non-volatile memory (NVM) can implement machine learning workload in an energy-efficient manner. Unfortunately, certain NVMs such as phase change memory (PCM) require high voltages for correct operation. These voltages are supplied from an on-chip charge pump. If the charge pump is activated too frequently, its internal CMOS devices do not recover from stress, accelerating their aging and leading to negative bias temperature instability (NBTI) generated defects. Forcefully discharging the stressed charge pump can lower the aging rate of its CMOS devices, but makes the neuromorphic hardware unavailable to perform computations while its charge pump is being discharged. This negatively impacts performance such as latency and accuracy of the machine learning workload being executed. In this letter, we propose a novel framework to exploit workload-specific performance and lifetime trade-offs in neuromorphic computing. Our framework first extracts the precise times at which a charge pump in the hardware is activated to support neural computations within a workload. This timing information is then used with a characterized NBTI reliability model to estimate the charge pump's aging during the workload execution. We use our framework to evaluate workload-specific performance and reliability impacts of using 1) different SNN mapping strategies and 2) different charge pump discharge strategies. We show that our framework can be used by system designers to explore performance and reliability trade-offs early in the design of neuromorphic hardware such that appropriate reliability-oriented design margins can be set.

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

For sub-20-nm FinFET and nanowire (NW) complementary metal-oxide semiconductor (CMOS) devices, negative bias temperature instability (NBTI) is an important reliability issue and requires an accurate model to predict device and circuit performance. In this paper, we report a well-calibrated predictive and scalable compact Verilog-A-based compact model, integrated with an NBTI model for NW CMOS circuit simulation and design. The stress and recovery NBTI model for an Si NW field-effect transistor is obtained from experimental NW pMOSFETs using a range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar metal-oxide semiconductor field-effect transistors. This is attributed to its cylindrical gate structure, resulting in enhanced 2-D hydrogen diffusion and stress-induced Si/SiO2 traps. This emphasizes the need to evaluate NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: an inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, the interface states generation, inverter delay, and RO frequency degrade rapidly and saturate over the long-term 10-year lifetime. Finally, the design of the SRAM cell employing the multiwire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using the appropriate design configuration. This paper underscores the need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at the device and circuit level.

Superior Reliability of Junctionless pFinFETs by Reduced Oxide Electric Field

Superior reliability of junctionless (JL) compared with inversion-mode field-effect transistors (FETs) is experimentally demonstrated on bulk FinFET wafers. The reduced negative bias temperature instability (NBTI) of JL pFETs outperforms the previously reported best NBTI reliability data obtained with Si channel devices and guarantees 10-year lifetime at typical operating voltages and high temperature. This behavior is understood through the reduced oxide electric field and lessened interaction between charge carriers and oxide traps during device operation. These findings encourage the investigation of JL devices with alternative channels as a promising alternative for 7-nm technology nodes meeting reliability targets.

Experimental Study on NBTI Degradation Behaviors in Si pMOSFETs Under Compressive and Tensile Strains

In this letter, we experimentally investigated the effects of four types of strains, uniaxial tensile strain, uniaxial compressive strain, biaxial tensile strain, and biaxial compressive strain, on the negative bias temperature instability (NBTI) degradation behaviors of Si pMOSFETs. The strains were applied using a wafer bending system to avoid processing effects on the NBTI characteristics as a result of strain engineering. We confirm experimentally, for the first time, that both uniaxial and biaxial compressive strains are advantageous in terms of the NBTI improvement in Si pMOSFETs. However, the NBTI reliability was degraded under both uniaxial and biaxial tensile strains. These results could not be explained by considering only the gate leakage current change due to the strain. The strain-induced modulation of the interaction between the carriers and Si-H bonds at the interface must also be considered.

Negative Bias Temperature Instability in p-FinFETs With 45$^{\circ}$ Substrate Rotation

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

Improved NBTI reliability with sub-1-nanometer EOT ZrO2 gate dielectric compared with HfO2

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.

NBTI reliability on high- k metal-gate SiGe transistor and circuit performances

Negative-bias temperature instability (NBTI) on high- k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High- k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress.

Interface/Bulk Trap Recovery After Submelt Laser Anneal and the Impact to NBTI Reliability

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high- devices with TaN/TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness.

NBTI Reliability of P-Channel Transistors With Diamond-Like Carbon Liner Having Ultrahigh Compressive Stress

Negative bias temperature instability (NBTI) characteristics of p-channel field-effect transistors (p-FETs) with diamond-like carbon (DLC) liner stressor having ultrahigh compressive stress (~ 5 GPa) are investigated for the first time. Ultrafast measurement was employed for NBTI study. Power law slopes ranging from ~ 0.058 to ~ 0.072 are reported here. P-FETs with higher channel strain show greater threshold voltage shift (DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) and transconductance degradation than those with lower or no channel strain under the same NBT stress condition V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> . Strained p-FETs with Si S/D and DLC stressors are projected to have an NBTI lifetime of ten years at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -0.99 V using E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> power law lifetime extrapolation model or at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = -0.76 V using the exponential V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">stress</sub> model.

Impact of Gate-Induced Strain on MuGFET Reliability

Hot carrier injection (HCI) reliability and negative bias temperature instability (NBTI) of multiple-gate field-effect transistors (MuGFETs) with highly tensile metal gate electrodes were investigated. The results were compared with those from control devices with poly-Si gate electrodes. It was found that gate strain boosts performance without any detrimental effect on HCI or NBTI reliability, indicating MuGFET compatibility with strained silicon technology. The impact of fin width (W fin) scaling was also investigated. HCI reliability improves with W fin scaling, whereas NBTI reliability degrades with W fin scaling. The same W fin scaling trends were observed in both strained and unstrained devices.

The switch of the worst case on NBTI and hot-carrier reliability for 0.13 μm pMOSFETs

This investigation describes experiments on two sizes of p-channel metal-oxide-semiconductor field-effect-transistors (pMOSFETs), to study the negative bias temperature instability (NBTI) and hot-carrier (HC) induced degradation. This work demonstrates that the worst condition for pMOSFETs under HC tests occurs in CHC (channel HC, stressed at V g = V d) mode at high temperature. This study also shows that the worst degradation of pMOSFETs should occur in NBTI. This inference is based on a comparison of results for forward saturation current ( I ds,f) and reverse saturation current ( I ds,r) obtained in NBTI and HC tests.

Improvement of Negative-Bias-Temperature Instability in SiN -Capped p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Using Ultrathin HfO2 Buffer Layer

Characteristics of p-channel -capped metal-oxide-semiconductor field-effect transistors (PMOSFETs) with a thin buffer layer were investigated. The compressive strain in the channel was deliberately induced in this study by a capping layer over the gate using plasma-enhanced chemical vapor deposition (PECVD). Although a compressive capping effectively boosts the drive current of PMOSFET devices, its presence also worsens the negative bias temperature instability (NBTI) characteristics due to the high hydrogen content in the layer, which could diffuse into the channel region during the deposition process. To address this issue, the insertion of a thick buffer layer between the gate and capping is proposed and demonstrated to improve NBTI reliability without sacrificing the device performance enhancement.

Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs

Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction-Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-gate MOSFET geometries to estimate the NBTI reliability under several scaling scenarios. Unless the operating voltages are optimized for specific geometry of transistor cross section, the results imply worsened NBTI reliability for the future-generation devices based on the geometric interpretation of the NBTI degradation. A time-efficient and straightforward analysis is developed to predict the degradation. This compact model confirms the numerical simulations.

Evidence for Two Distinct Positive Trapped Charge Components in NBTI Stressed p-MOSFETs Employing Ultrathin CVD Silicon Nitride Gate Dielectric

Besides the generation of interface states and the associated positive trapped charge (N/sub tc1/), experimental results unambiguously show the generation of another positive trapped charge component (N/sub tc2/) during negative-bias temperature instability (NBTI) stressing of p-MOSFETs employing ultrathin silicon nitride gate dielectric. For a given gate stress voltage, N/sub tc2/ is generated at a much faster rate compared to N/sub tc1/. Under the pulsed gate condition studied, N/sub tc1/ could almost be completely annihilated, regardless of the NBTI stress voltage, whereas only partial annihilation of N/sub tc2/ is observed. This more resistant nature of N/sub tc2/ to post-stress relaxation has serious implications on the dynamic NBTI reliability of these p-MOSFETs.