Abstract
It has become more challenging to suppress the negative bias temperature instability (NBTI) in advanced FinFET technology which is largely originated from the dielectric/channel interface in HKMG structure. In this work, we report the experimental approach to mitigate the NBTI in 14-nm FinFET devices through HKMG thermal processing optimization. The NBTI reliability degradation arises from the formation of defective SiO<sub>2</sub> interlayer and the interface traps based on a quantitative analysis. Using optimized post-dielectric annealing (PDA) and post-Si-cap annealing (PCA) processing, an improved balance between the SiO<sub>2</sub> interlayer quality and high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula>/SiO<sub>2</sub> interface trap density has been achieved. The NBTI <inline-formula> <tex-math notation="LaTeX">${V}_{t}$ </tex-math></inline-formula> shift and device local variation are effectively suppressed. This provides an instructive pathway to enhance the NBTI reliability in FinFET through process optimization approaches.
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