NBTI and HCI Aging Prediction and Reliability Screening During Production Test

Abstract

With the semiconductor manufacturing technology approaching to 14 nm and below, the reliability of IC is challenged, as the speed of CMOS or FinFET is degraded by the aging mechanisms, including negative bias temperature instability (NBTI) and hot carrier injection (HCI). Furthermore, significant process variations differ the aging degradation rate of each individual IC, which causes significant failure time differences even for the ICs belonging to the same lot. Therefore, to select devices for the applications with various reliability requirements, it is necessary to conduct efficient predictive reliability screening during production test at time-zero. In this article, a fast time-zero aging prediction and predictive screening methodology based on a novel on-chip architecture named ZeroScreen is proposed. The pattern-based aging screening time is limited to 8.14 ms per device considering 50-MHz test clock frequency and 6.6- $\mu \text{s}$ automatic test equipment (ATE) voltage settling time. In the experiment, fresh 45-nm FPGA devices and 130-nm ASIC chips are projected into four reliability bins with ZeroScreen-based aging prediction at time-zero. According to the silicon data, the reliability screening errors of ZeroScreen for the 45-nm FPGA chips are less than 6.5% and 4.3% for static and dynamic stress cases, respectively. And the screening errors for the 130 nm ASIC chips are close to 0, for both static and dynamic stress cases.