Negative Bias Temperature Instability Research Articles

Simulation and modelling of long term reliability of digital circuits implemented in FPGA

In this work, we report on the development of a methodology for long term reliability analysis of digital circuits implemented in FPGA. For this, a simulation environment for FPGA has been extended using Python to introduce aging. The aging laws for Look-Up Tables have been integrated by introducing additional variables and equations. They accurately describe the drifts in the propagation time caused by Hot Carrier Injection and Negative Bias Temperature Instability degradation mechanisms. An analytical model of the failure time of the digital circuit as a function of the clock frequency has been proposed based on the aging law parameters. Finally, the developed methodology has been applied to a CORDIC circuit implemented in FPGA.

Negative bias temperature instability in SOI‐like p‐type metal oxide semiconductor devices

A silicon on insulator (SOI)-like bulk silicon (SLBS) MOSFET has been recently reported. An ‘n/p-/n+’ structure was contained in SLBS P Metal Oxide Semiconductor (PMOS) device, with ‘p-’ is made of 4H-SiC. This p-layer is fully depleted. In this work, negative bias temperature instability (NBTI) of SLBS pMOSFET is studied and compared with that in bulk and Fully Depleted (FD) SOI PMOSFET. The effects of stress temperature and body bias on NBTI of SLBS device are also be studied in this work. The work demonstrates an advantage of SLBS over bulk and FD SOI devices.

Performance and V TH Stability in E-Mode GaN Fully Recessed MIS-FETs and Partially Recessed MIS-HEMTs With LPCVD-SiN x /PECVD-SiN x Gate Dielectric Stack

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiN x /PECVD-SiN x ) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance ( ${R}_{ \mathrm{ON}}$ ), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET.

NMOS only Schmitt trigger circuit for NBTI resilient CMOS circuits

A novel N-type MOS (NMOS) only Schmitt trigger with voltage booster (NST-VB) circuit is presented. The proposed NST-VB circuit uses NMOS transistors in both pull-up and pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the circuit. The proposed circuit is less affected by both inter-die and intra-die process variations in consequence of NMOS only structure. Owing to NBTI, the increase in delay for the proposed NST-VB circuit is only 0.47% as compared with 7.2% for conventional Schmitt trigger after the stress time of three years. For the viability of the proposed circuit figure of merit (FOM) is used as a performance metric and it is found that the proposed circuit has 15.35 × and 3.53 × improved FOM as compared with the conventional Schmitt trigger and NMOS inverter, respectively.

Impact of NBTI Stress on VDMOSFET Regions

In this paper, we investigate the impact of negative bias temperature instability (NBTI) degradation on both channel and drain regions, of commercial power double diffused MOS transistor (VDMOSFET), using capacitance-voltage method (C-V). We report that the degradation is important at channel (drain) region in p-channel VDMOSFET (n-channel VDMOSFET). That means that the phosphorus doped region (n-type) is more sensitive to NBTI stress.

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.

On-Chip Adaptive Body Bias for Reducing the Impact of NBTI on 6T SRAM Cells

Negative bias temperature instability (NBTI) is a major reliability issue with the scaled devices at elevated temperature. The effect of NBTI increases with the time, and it increases the threshold voltage of pMOS. In this paper, an on-chip adaptive body bias (O-ABB) circuit to compensate the degradation due to NBTI aging is presented. The O-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin, and word line write margin (WLWM). The O-ABB consists of standby leakage current ( ${I}_{{ddq}}$ ) sensor circuit, decision circuit, and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of ten years NBTI aging. The proposed O-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM, and WLWM decreases by 10.55%, 8.55%, and 3.25%, respectively, in the absence of O-ABB, whereas hold SNM, read SNM, and WLWM decreases by only 0.47%, 1.15%, and 0.62%, respectively, if O-ABB is used to compensate the degradation.

Identification of Interface States and Shallow and Deep Hole Traps under NBTI Stress using Fast, Normal, and Charge-pumping Measurement Techniques

We propose an identification method of interface state density (NSUBit/SUB), shallow hole trap density (NSUBht.S/SUB), and deep hole trap density (NSUBht.D/SUB), which were generated by negative bias temperature instability (NBTI) stress. NSUBht.S/SUB, NSUBht.D/SUB, and Nit were decoupled into recoverable traps and permanent traps through the proposed method. We analyzed which traps among hole-trapping charges and interface states constitute the main permanent damage component and have the largest power-law exponent with various stress voltages and temperatures. The power-law exponent of each trap showed that NSUBht.D/SUB and NSUBit/SUB lead to considerable timedependent degradation. Moreover, based on the recovery characteristics of each trap, 31% of the total traps became permanent traps and 77% of the permanent traps were NSUBht.D/SUB, which implies that NSUBht.D/SUB is a crucial factor, constituting the main component of the permanent damage.

Revisited study of fluorine implantation impact on negative bias temperature instability for input/output device of automotive micro controller unit

We investigate the effect of fluorine implanted in the polycrystalline silicon (poly-Si) gate and source/drain (S/D) region on negative bias temperature instability (NBTI) improvement. It is found that there is a trade-off implantation energy dependence of NBTI between fluorine in the poly-Si gate and that in the S/D region. Fluorine implanted in the poly-Si gate contributes to NBTI improvement under low energy implantation. On the other hand, NBTI is improved by fluorine implanted in the S/D region under high energy. We propose that the two-step implantation process with high and low energy is the optimum condition for NBTI improvement.

Evaluation of plasma-induced damage and bias temperature instability depending on type of antenna layer using current-starved ring oscillators

Plasma-induced damage (PID) and bias temperature instability (BTI) are inevitable reliability issues that degrade the performance of transistors. In this study, PID and BTI, depending on the type of antenna layer, are evaluated in current-starved ring oscillators (ROs) to separate degradations in PMOS and NMOS transistors in a 65 nm silicon-on-insulator (SOI) process. Oscillation frequencies of ROs fluctuate with the performance of MOSFET switches between power/ground rails and virtual power/ground nodes. The initial frequencies of ROs with PMOS switches having antennas on upper layers decrease. However, those with NMOS switches become higher than those without PID because high-k dielectrics are damaged by positive charges. The degradation induced by negative BTI (NBTI) in PMOS is 1.5 times larger than that induced by positive BTI (PBTI) in NMOS. However, both NBTI- and PBTI-induced degradations are the same among different antenna layers. The frequency fluctuation caused by PID is converted to threshold voltage shifts by circuit simulations. Threshold voltages shift by 8.4 and 11% owing to PID in PMOS and NMOS transistors, respectively.

Aging analysis of high performance FinFET flip-flop under Dynamic NBTI simulation configuration

A mechanism known as Negative-bias Temperature Instability (NBTI) degrades a main electrical parameters of a circuit especially in terms of performance. So far, the circuit design available at present are only focussed on high performance circuit without considering the circuit reliability and robustness. In this paper, the main circuit performances of high performance FinFET flip-flop such as delay time, and power were studied with the presence of the NBTI degradation. The aging analysis was verified using a 16nm High Performance Predictive Technology Model (PTM) based on different commands available at Synopsys HSPICE. The results shown that the circuit under the longer dynamic NBTI simulation produces the highest impact in the increasing of gate delay and decrease in the average power reduction from a fresh simulation until the aged stress time under a nominal condition. In addition, the circuit performance under a varied stress condition such as temperature and negative stress gate bias were also studied.

A Fast $V_{th}$ Measurement (FVM) Technique for NBTI Behavior Characterization

In this letter, a novel fast threshold voltage ( ${V}_{th}$ ) measurement (FVM) technique is proposed and demonstrated, which could perform ${I}$ – ${V}$ characterization of MOSFETs within 1 ns. With the advanced FVM technique, down to 1-ns negative biased temperature instability (NBTI) characterization was successfully carried out for Si pFinFETs at 14-nm technology node. It is experimentally confirmed that the nano-second-level fast recoverable traps, which are generated during NBTI stress, could lead to the underestimation of ${V}_{th}$ degradation under micro-second-level measurement speed. Furthermore, it is found that even when the ${V}_{th}$ measurement is performed within 1 ns after the stress removal, it is still not fast enough to be the real recovery-free measurement. Yet, with the proposed FVM technique, NBTI characteristics could be characterized more accurately and closer to its intrinsic behaviors.

NBTI and Power Reduction Using a Workload-Aware Supply Voltage Assignment Approach

Supply voltage assignment (SVA) can alleviate the performance aging induced by the negative bias temperature instability (NBTI) effect. However, due to the random characteristic of an actual system workload, it is difficult to estimate the aging rate and control the supply voltage reasonably. To solve this problem, we present a workload-aware SVA method (WSVA) that encapsulates the workload change into the aging estimation using an LUT-based approach. Moreover, an NBTI and leakage co-optimization strategy based on an integer linear programming (ILP) approach is proposed to obtain the optimal input vector in standby mode. Simulation experiments on multiple benchmark circuits demonstrate that the LUT-based approach can track the dynamic change of the workload online and provide an accurate aging estimate for SVA with little computation cost. Compared with the SVA method without considering the workload, the proposed aging estimation approach and the optimal input vector selection strategy in the WSVA framework can enable the CMOS circuit conserve additional power dissipation while guaranteeing the performance requirements.

BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation

A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc–ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

A review of pulsed NBTI in P-channel power VDMOSFETs

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide-semiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

Integrated modeling of Self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern integrated circuits

The evolution of transistor topology from planar to confined geometry transistors (i.e., FinFET, Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20nm integrated circuits (ICs), but only at the expense of increased power density and thermal resistance. Thus, self-heating effect (SHE) has become a critical issue for performance/reliability of ICs. Indeed, temperature is one of the most important factors determining ICs reliability, such as Negative Bias Temperature Instability (NBTI), Hot Carrier Injection (HCI), and Electromigration (EM). Therefore, an accurate SHE model is essential for predictive, reliability-aware ICs design. Although SHE is collectively determined by the thermal resistances/capacitances associated with various layers of an IC, most researchers focus on isolated components within the hierarchy (i.e., a single transistor, few specific circuit configurations, or specialized package type). This fragmented approach makes it difficult to verify the implications of SHE on performance and reliability of ICs based on confined geometry transistors. In this paper, we combine theoretical modeling and systematic transistor characterization to extract thermal parameters at the transistor level to demonstrate the importance of multi-time constant thermal circuits to predict the spatio-temporal SHE in modern sub-20nm transistors. Based on the refined Berkeley Short-channel IGFET Model Common Multi-Gate (BSIM-CMG) model, we examine SHE in typical digital circuits (e.g., ring oscillator) and analog circuits (e.g., two-stage operational amplifier) by Verilog-A based HSPICE simulation. Similarly, we develop a physics-based thermal compact model for packaged ICs using an effective media approximation for the Back End Of Line (BEOL) interconnects and ICs packaging. We integrate these components to investigate SHE behavior implication on ICs reliability and explain why one must adopt various (biomimetic) strategies to improve the lifetime of self-heated ICs.

Investigation on NBTI-induced dynamic variability in nanoscale CMOS devices: Modeling, experimental evidence, and impact on circuits

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV+CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.

Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions

Threshold voltage shift ( $\Delta {\text V}_{\text T}$ ) due to negative-bias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps ( $\Delta {\text V}_{\text {IT}}$ ), hole trapping in preexisting ( $\Delta {\text V}_{\text {HT}}$ ), and generation of new ( $\Delta {\text V}_{\text {OT}}$ ) bulk insulator traps is used to quantify measured data. The model can explain dc stress and recovery data over an extended temperature range (−40 °C to 150 °C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of $\Delta {\text V}_{\text {IT}}$ , $\Delta {\text V}_{\text {HT}}$ , and $\Delta {\text V}_{\text {OT}}$ , and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods.

Negative bias temperature instability in strained-Si p-MOSFETs

Strained-Si p-channel metal oxide semiconductor field effect transistors (MOSFETs) have become the performance boosters beyond 90 nm technology node. Reliability study of these devices is essential as only a few reports are available on this. In this work, we have explored the degradation mechanisms in these devices due to negative bias temperature instability (NBTI). Device simulation results have been calibrated with reported experimental data and a good agreement is observed. The reliability study of these devices has been performed using the two-stage model for defect creation. Study of the drain current degradation and comparison of threshold voltage shift after stressing between the strained-Si and Si channel p-MOSFETs have been performed. The threshold voltage degradation in strained-Si channel p-MOSFETs is found to be considerably higher than that in the bulk-Si devices due to higher fixed oxide charge and interface trap densities at the strained-Si/SiO2 interface.