Narrow Fin Devices Research Articles

TID Response of Bulk Si PMOS FinFETs: Bias, Fin Width, and Orientation Dependence

The total ionizing dose (TID) response of bulk Si PMOS FinFETs with two fin widths and two types of fin orientation (standard and 45° rotated) is experimentally investigated under four irradiation bias conditions. The bias dependence of bulk Si PMOS FinFETs is demonstrated. The ON-bias configuration is found to be the worst irradiation bias condition. Besides, fin width dependence is illustrated. Narrow fin devices show larger threshold voltage ( $V_{{\text {th}}}$ ) shift after irradiation compared with wide fin devices. Furthermore, the fin orientation dependence of the TID response of bulk Si PMOS FinFETs is investigated. The 45° rotated transistors ( $\langle 100\rangle $ Fin) illustrate smaller irradiation-induced $V_{{\text {th}}}$ shift and transconductance ( $g_{m}$ ) decrease compared with standard transistors ( $\langle 110\rangle $ Fin). This orientation dependence is attributed to the oxidation rate and carrier mobility dependence of fin orientation. The results may deepen the understanding of the TID effect of bulk Si PMOS FinFET and offer an idea for future radiation-hardened FinFET integrated circuit (IC) fabrication.

Superior Transient Response to Heavy-Ion Irradiation by N-Channel SOI-iFinFETs

In this paper, we for the first time report the transient response of SOI-iFinFETs under heavy-ion radiation conditions. Using calibrated 3-D TCAD simulations, we analyze the radiation performance of advanced multi-gate devices such as SOI-FinFET and iFinFETs, which conform to 14 nm technology node. The transient response of FinFETs, and iFinFETs with varying number of inserted oxide regions, is reported under heavy-ion irradiation. The effective fin width and gate length scaling has also been reported for FinFET and iFinFETs under heavy-ion irradiation. Our results show that iFinFETs are better suited for heavy-ion radiation environments as compared to FinFETs due to the presence of inserted oxide in between the fin regions. The iFinFETs show up to 28% less peak drain current generated due to heavy-ion with LET = 10 MeV-cm2/mg as compared to FinFETs. We also show that iFinFET architecture brings more advantage to radiation performance over conventional FinFETs for narrow fin devices, while gate length scaling has similar radiation response for both FinFET and iFinFETs.

Invited; Ge-on-Insulator MOSFETs for High-Performance and 3D-LSI Applications

Germanium is recognized as new channel material to be introduced in near future CMOS technologies. The advantages are the high hole mobility, the high p-type dopant activation and the low contact resistivity, whereas the smaller band gap results in higher off state current than Si devices. Therefore, Ge-MOSFETs are considered to be most promising to use as a pMOS counterpart of III-V nMOSFETs for high-performance CMOS devices. In order to suppress the off leakage current, Ge-on-insulator (GeOI) substrates may be preferable than bulk substrates. On the other hand, the low thermal budget of the fabrication processes can provide another opportunity for Ge devices. Sequentially stackable COMS devices may be a possible application for 3D-LSIs instead of a TSV technology. Poly-Ge CMOS devices on insulating layers may be one of solutions for the 3D-LSIs. In this paper, electrical properties and processes of high performance strained Ge nanowire pMOSFETs and poly-Ge trigate pFETs both on buried oxide (SiO2) layers, which are dedicated for the former and the latter applications, respectively, are presented.The Ge nanowire devices were formed by a two-step Ge condensation technique for the channels and a self-aligned NiGe process for the source and drain [1]. A compressive strain of around 4% along the channel direction of <110> was observed after the condensation process, suggesting that no relaxation of the misfit strain between Si and Ge was occurred. A significantly high-hole mobility of 1922 cm2/Vs has been achieved thanks to the high strain and the good interfacial quality between the gate insulator and the Ge channel. Ion/Ioff over 105 has also been attained for the Ge nanowire pMOSFET with a gate length (Lg ) of 45 nm. Poly-Ge junction-less (JL) pFETs with a Lg down to 40 nm were formed on a SiO2 layer on a Si substrate [2]. The poly-Ge channel was naturally p-type with a hole concentration around 5x1018 cm-3 presumably due to the crystalline defects. No additional doping has been done. A high Ion/Ioff of around 105 was observed for narrow fin (7 nm) devices, although wider devices (>11 nm) exhibited degraded cut-off characteristics. We also found that the current drivability was drastically improved by using a flash lamp annealing (FLA) method due to the high hole mobility in the poly-Ge channel. A drain current value of 280 μA/μm was achieved at Vd =-1 V for the Lg =80 nm device [3], which is comparable with that of a mono-crystalline Si-pMOSFET of 130-nm technology node.In summary, two types of GeOI pMOSFETs for near-future high-performance logic CMOS-ICs and low-cost stackable applications were demonstrated. In both types of devices, the GeOI platform and non-planar gate configurations are key technologies to achieve sufficiently high Ion/Ioff values, which is one of major concerns to implement Ge devices into markets. Acknowledgement This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP).

(Invited) Replacement Metal Gate/High-k Last Technology for Aggressively Scaled Planar and FinFET-Based Devices

For (sub-)22nm nodes, new device architectures such as multi-gate FinFET-based devices have long been regarded an attractive option to allow further CMOS scaling thanks to their improved electrostatics and reduced VT-variability [1]. In this work, we address the need for processes compatible with their 3D-architecture by reporting on a novel EWF engineering approach [2] which enables wide VT-modulation (>500mV ΔVT in narrow fin (WFin≥5nm), triple-gate FinFETs in Fig. 1), with no EOT nor JG penalty, improved mobility and BTI, excellent mismatch performance, up to ~6.3× reduced noise (Fig. 2), and minimized parasitic Rgate and σ(Rgate), while suitable also for scaled planar FETs where larger EWF shifts from mid-gap to reach low or high-VT targets are needed. It relies on diffusion mechanisms in the gate stack, namely controlled Al diffusion from the fill-metal (CoxAly) through an ultra-thin TaN layer into the TiN covering the high-k dielectric (e.g., HfO2), and fine-tuned TiN/TaN thicknesses. Since Al-rich TiN has a more n-type EWF, stacks with higher amount of Al diffused into TiN translate into lower EWF values (→ lower NMOS VT), with TiN growth optimized for enhanced (NMOS) or inhibited (PMOS) Al diffusion into/through it.Focusing next on gate dielectric scaling, we report a thorough evaluation of the impact of HfO2 doping [3], post high-k deposition thermal (PDA) and SF6-based plasma treatments [4,5] for planar vs. FinFET devices with different Si crystal orientations for the fin top and sidewall surfaces, providing a deeper insight into underlying degradation mechanisms. Higher k-value HfO2 (k~30) is achieved by introducing a metallic dopant during HfO2 growth, followed by an 800°C PDA which crystallizes HfO2 into its cubic phase. Up to 103× JG reduction at ~9.7Å EOT and net performance (ION) and reliability (BTI, TDDB) improvements when normalized to JG make this material attractive for low-power applications. F incorporation into the gate stack through exposure of HfO2 to a SF6-plasma results in substantially reduced Nit and noise values, improved mobility, and no EOT penalty down to narrow fin devices (WFin≥5nm), mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations due to defects passivation by Hf-F and Si-F bonds formation. The plasma was optimized by increasing the number of ions reaching the bottom of narrow, high aspect-ratio gate trenches such that it can be used to incorporate F in the gate stack and to selectively remove the p-EWF/barrier metals (TiN/TaN) from NMOS areas in a simplified, highly scalable dual-EWF metal CMOS scheme [5] suitable for 2D and 3D device architectures and which maximizes the space for gate metallization. NBTI lifetime improvement with SF6 at 125°C is however fairly modest in the (sub-)1nm EOT regime, substantially increasing upon PDA introduction in the process flow, and for higher PDA temperatures (760°C→800°C). PDA devices exhibit reduced JG (enabling nFETs with ~10× lower JG at given VT) and show considerably smaller total effective trap density values, despite an increase in Nit (~1.4-1.8×), thanks to reduced bulk traps/defects. The latter seem thus to play a key and dominant role in NBTI for ultra-thin EOT, being mostly pre-existing defects contributing to charge trapping and de-trapping during stress and relaxation as inferred by the larger recoverable (R) vs. permanent BTI degradation components, calculated assuming universality of relaxation. Less steep R vs.stress time dependence in PDA devices also indicate less generation of new defects during stress, with improved hot-carrier immunity due to less charge trapping into bulk defects corroborating reduced presence of the latter. Further reliability gain is obtained for PMOS with (100) fin sidewalls in agreement with LF-noise results (Fig. 2).

Fin Width and Gate Length Dependences of Charge Pumping and DCIV Currents in Floating-Body SOI MOSFETs

We have evaluated the effects of device geometry and frequency on DCIV and ACIV (charge pumping) currents in development-stage SOI finFETs with floating bodies that are built in two process technologies. Both the DCIV and ACIV currents are much smaller in devices for which the gate length exceeds ~100 nm or the fin width exceeds ~70 nm. ACIV currents are approximately linear with frequency up to ~300 kHz for the devices and measurement conditions used in this study. ACIV estimates of effective interface-trap densities for relatively short-channel, narrow-fin devices in each technology are ~4 × 1011 cm-2.

Origin of the low-frequency noise in n-channel FinFETs

The origin of the low-frequency noise is investigated in n-channel fin-shaped field-effect transistors (FinFETs) in terms of the channel length and fin width. In long-channel and wide fin devices, the spectra are dominated by 1/f noise due to carrier number fluctuation, correlated with mobility fluctuations. In long-channel and narrow fin devices, the spectra are composed of both 1/f and excess generation–recombination (g–r) noise components. Analysis of the g–r noise parameters lead to the conclusion that the g–r noise originates from traps in the sidewall gate oxides and in a depletion region near the sidewall interfaces. In short-channel devices, the spectra show 1/f behavior in the weak inversion described by carrier number fluctuations and g–r noise component in the low drain current region, possibly originating from the source and drain contacts process.

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL. On the other hand, the impact of the gate dielectric on the GIDL for p- channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed.

Proton-Induced Mobility Degradation in FinFETs With Stressor Layers and Strained SOI Substrates

Proton irradiation effects on fin-type field effect transistors (FinFETs) are examined from the viewpoint of their electrical-performance parameter of mobility. They are fabricated with various types of combination of strain/stress techniques to control their mobilities. The base stress level is globally modified by means of nonstrained or strained silicon-on-insulator wafers. Some process splits, additionally, receive a local strain tuning with a contact-etch-stop layer (CESL). Both <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> - and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -type FinFETs are evaluated. A 60-MeV proton irradiation with a fluence of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> p/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> leads to mobility changes for wide-fin samples: degradation for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -type and enhancement for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> -type. These mobility variations can be explained with a change in the number of charged interface traps at the Si and buried-oxide interface. Narrow-fin devices exhibit mobility changes unnoticeable statistically. A comparison with previous studies indicates an elevated source/drain structure plays a role in this mobility preservation. Although the mobility is kept intact in the narrow-fin samples, a close investigation based on a two channel-component model can reveal noticeable mobility variations at a component level. In this study, observed mobility changes are complex depending on the adopted stress techniques as well as process parameters and cannot be explained by the stress levels simply.

Influence of Back-Gate Bias and Process Conditions on the Gamma Degradation of the Transconductance of MuGFETs

The gamma radiation-induced variation of the transconductance in the subthreshold region is studied for different back-gate voltages and for different kinds of SOI MuGFETs: devices with and without selective epitaxial growth (SEG) and 45 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> rotated transistors. Wide fin devices show a larger degradation when the back-gate is grounded. The back-channel of narrow fin transistors, on the other hand, needs to be inverted before degradation in the transconductance is observed. The radiation behavior of the transconductance is similar for devices with and without SEG. It is shown that the maximum variation in transconductance correlates with the mobility for narrow fin devices. This mobility varies when the transistor is rotated. For wide fin devices this correlation is not as strong.

Analysis of the Interface Trap Density in SOI FinFETs with Different TiN Gate Electrode Thickness through Charge Pumping Technique

This work presents the analysis of the interface trap density in triple-gate silicon-on-insulator FinFET gated-diode structures with different TiN gate electrode thickness and fin widths by using the charge pumping technique. It is shown that a thicker metal gate corresponds with more traps. The fin width comparison shows that narrow fin devices exhibit a higher interface trap density due to the (110) sidewall contribution.

Advanced FinFET Devices for Sub-32nm Technology Nodes: Characteristics and Integration Challenges

We report a comprehensive evaluation and overview of the latest developments and technology challenges of FinFET-based devices. They offer improved electrostatics and steeper sub-threshold slopes, attractive for enabling further CMOS scaling, but can also suffer from higher parasitic resistance and parasitic capacitance for narrow Fin devices. Critical solutions to minimize the impact of the latter are here addressed, demonstrating their viability for replacing planar CMOS devices. Multiple-VT CMOS can be achieved with capping technology, with aggressively scaled Ring Oscillators (RO) and SRAM cells showing excellent performance and matching behavior.

Multi-gate devices for the 32 nm technology node and beyond: Challenges for Selective Epitaxial Growth

This work will focus on the use of Selective Epitaxial Growth (SEG) of Si and SiGe in multi-gate devices. We will demonstrate the necessity of using SEG in the processing of these narrow fin devices. Reductions of the source/drain resistance and Gate Induced Drain Leakage (GIDL) are the main advantages of using SEG. Although the use of SiGe SEG has little impact as mobility booster in narrow fin pMOS devices, it provides a significant reduction in contact resistance.

Modelling the Back-Gate Coupling effect in Triple-, Π- and Ω-Gate FETs

In multiple-gate devices, coupling effects due to the 3-D architecture modify the electrical characteristics of the transistor. In this paper, electrical measurements have been carried out in order to examine the role of the back-gate voltage. In agreement with numerical simulations, it is shown that the back-gate influence is reduced for narrow devices due to a strong coupling between the different faces of the main gate. In narrow Fin devices, the Pi- and Omega-shapes of the gate provide an excellent electrostatic control of the field lines and potential, both in the buried oxide and in the silicon channel. The radiation-induced charge trapping in the BOX underneath the channel can be then much limited: narrow Fin devices exhibit a higher tolerance to ionizing radiations than its single-gate counterparts. Additionally, it is shown that the 2D dimensional coupling in these structures can be analytical calculated for Triple- and Pi-gate FETs. These models are compared with numerical simulations and show a very good agreement.

Performance improvement of tall triple gate devices with strained SiN layers

In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.

Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode

In this work, the effective mobility in n- and p-channel FinFETS with silicon oxynitride and HfO2 gate dielectrics and TaN gate electrode is studied as a function of the inversion charge density using a split C-V technique. The mobility behavior in narrow-fin devices is compared to that in quasi-planar wide-fin devices, and the mechanisms responsible for the observed differences are discussed. The devices with HfO2 and silicon oxynitride gate dielectrics exhibit similar mobility behavior.

Shift and ratio method revisited: extraction of the fin width in multi-gate devices

In this work, we extend the modified shift and ratio method, originally used for extracting the effective channel length in standard short channel MOSFETs, to the extraction of the fin width in FINFET devices. Using devices with different fin widths, the electrical width of the devices can be extracted. The method is adapted in such a way that it takes into account the difference in mobility due to the different crystal orientation of the fin sidewalls and top surface, the width dependence of the threshold voltage and the influence of the increasing source/drain resistance for narrow fin devices.