Abstract

In multiple-gate devices, coupling effects due to the 3-D architecture modify the electrical characteristics of the transistor. In this paper, electrical measurements have been carried out in order to examine the role of the back-gate voltage. In agreement with numerical simulations, it is shown that the back-gate influence is reduced for narrow devices due to a strong coupling between the different faces of the main gate. In narrow Fin devices, the Pi- and Omega-shapes of the gate provide an excellent electrostatic control of the field lines and potential, both in the buried oxide and in the silicon channel. The radiation-induced charge trapping in the BOX underneath the channel can be then much limited: narrow Fin devices exhibit a higher tolerance to ionizing radiations than its single-gate counterparts. Additionally, it is shown that the 2D dimensional coupling in these structures can be analytical calculated for Triple- and Pi-gate FETs. These models are compared with numerical simulations and show a very good agreement.

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