Nanosheet Field Effect Research Articles

Investigation of triple vertically stacked nanosheet FET with geometric variability at advanced technology node: DC, analog and RF performance benchmarking

Abstract This paper presents an in-depth analysis of the digital, analog, and radio frequency (RF) performance metrics of three-dimensional gate-all-around (GAA) triple nanosheet fieldeffect transistor (NSFET) designed for the 5 nm technology node. By optimizing the key physical dimensions of the NSFET specifically, a nanosheet width of 20 nm, thickness of 5 nm, and gate length of 12 nm, significant improvements in device performance were achieved. The optimized NSFET demonstrated a remarkable Ion/Ioff ratio of 2.99×10⁶, a low subthreshold swing of 65.63 mV/dec, and minimal drain-induced barrier lowering (DIBL) of 21.94 mV/V. Additionally, the device exhibited enhanced transconductance (gm = 3.2×10⁻⁴ S), contributing to a high intrinsic gain (Avo = 47 dB). In terms of RF performance, the NSFET achieved a cut-off frequency (fT) of 394 GHz and a maximum oscillation frequency (fmax) of 491 GHz, showcasing its potential for high-frequency applications. These results highlight the superior performance of NSFETs over FinFETs, making them a promising candidate for digital, analog, and RF circuit designs in advanced sub-5 nm technology nodes. The combination of excellent electrical characteristics and high-frequency performance positions NSFETs as a leading solution for next-generation integrated circuits.

Self-heating optimisation of nanosheet field effect transistor performance with physics-based calibrated simulation setup

Self-heating optimisation of nanosheet field effect transistor performance with physics-based calibrated simulation setup

Analytical Multistage Thermal Resistance Model for NSFET Self-heating Effects

—As semiconductor technology nodes continue to scale down to 3 nm, the self-heating effect in Gate-All-Around Nanosheet Field-Effect Transistors (GAA-NSFETs) has become a significant concern. This issue arises due to the complex interaction between device dimensions, material properties, and thermal management, which can lead to performance degradation and reliability challenges in advanced transistor designs. This paper aims to investigate the self-heating phenomenon in three-stacked nanosheet FETs and to develop a novel thermal resistance model that accurately captures the thermal behavior of these devices. The goal is to create a reliable framework for analyzing and mitigating self-heating effects in nanosheet-based transistors. We employed TCAD and SPICE simulations to analyze the self-heating effect in nanosheet FETs. A new multi-stage thermal resistance model (TRM), incorporating both thermal resistance (Rₜₕ) and thermal capacitance (Cₜₕ), was developed within the Berkeley Short-channel IGFET Model-Common MultiGate (BSIM-CMG) framework. Model accuracy was ensured by fitting the simulated ID-VG curves to experimental data, followed by parameter extraction and calibration based on self-heating evaluations. The proposed multi-stage Rₜₕ model demonstrated strong agreement with the simulation results, providing an accurate representation of the thermal behavior in three-stacked nanosheet FETs. This model offers a robust tool for analyzing self-heating effects in advanced nanosheet devices and can be used to guide the design and optimization of future low-power, high-performance transistors.

Multiphysics Simulation of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in Gate-All-Around Nanosheet Field Effect Transistors

Multiphysics Simulation of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in Gate-All-Around Nanosheet Field Effect Transistors

Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device

This paper presents a simulation study on a 12 nm Gate-all-around n-type Metal Oxide Semiconductor (GAA-nMOSFET), investigating the effects of temperature variations and doping concentrations. The structure of the device has three fins, and the channel is surrounded by gate material to reduce the short channel effect (SCE) and electrostatic capacitance. Various parameters such as threshold voltage (Vth), Ion/Ioff ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS) are evaluated at different temperatures 250 K, 300 K, and 350 K, doping concentrations of 1016cm−3, 1017cm−3, and 1018cm−3, with a high voltage of 0.65V. At a temperature of 250 K, in comparison to the 1016cm−3 doping concentration attention, the Vth is observed to be 0.31V, while the Ion/Ioff ratio is measured at 0.33e−14. Moreover, the DIBL experiences a reduction of 25 %, whereas the SS increases by 76 %. Furthermore, when the temperature is raised to 300 K relative to the 1017cm−3 doping concentration, the Vth increases to 0.32 V, and the Ion/Ioff current ratio rises to 0.45e−14. Meanwhile, the DIBL experiences a decrease of 20 %, and the SS increases by 71 %. Finally, at a temperature of 350 K concerning 1018cm−3 doping concentration, the Vth is measured at 0.34 V, and the Ion/Ioff current ratio reaches 0.47e−14 Concurrently, the DIBL shows a decrease of 28 %, While the SS increases to 79 %. To reduce electrostatic capacitance and leakage current, the use of a high-k dielectric material in a GAA-nMOSFET device is investigated. Improved performance traits such as decreased SCE, low DIBL, and strong SS are displayed. Additionally, the connection between threshold voltage and doping concentration is investigated. The effect of temperature variations and doping concentration on many essential characteristics of 12 nm GAA-nMOSFET shows the potential benefits of the device's unique architecture and material. The conclusions are supported through circuit schematics, simulations, and experimental data in this article.

Design and performance analysis of double gate vertically stacked MoS2 nanosheet field effect transistor

In this work we report a vertically stacked nanosheet Field Effect Transistor (NSFET) in double gate configuration using transition metal dichalcogenide (TMD) based molybdenum disulphide (MoS2) as the conducting channel. The performance of the NSFET is analysed for number of channels, different channel thickness, different source/drain contacts. The performance of the device at different temperatures (T) also analysed. The proposed NSFET with three vertically stacked channels, exhibits a ON current (ION) of 30.6 μA μm−1, Subthreshold swing (SS) of 69 mV/dec and ON to OFF current ratio of more than 108 at Vds = 1V. Further the ION can be improved with multi-layer channel thickness. The performance of the vertically stacked MoS2 NSFET in junction less (JL) and inversion mode (IM) is compared, it is concluded from the simulations that JL vertically stacked MoS2 NSFET more immune to short channel effects such as threshold voltage (Vth) roll-off and drain induced barrier lowering (DIBL).

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers.

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors.

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

Ultrasensitive 3D Stacked Silicon Nanosheet Field-Effect Transistor Biosensor with Overcoming Debye Shielding Effect for Detection of DNA.

Silicon nanowire field effect (SiNW-FET) biosensors have been successfully used in the detection of nucleic acids, proteins and other molecules owing to their advantages of ultra-high sensitivity, high specificity, and label-free and immediate response. However, the presence of the Debye shielding effect in semiconductor devices severely reduces their detection sensitivity. In this paper, a three-dimensional stacked silicon nanosheet FET (3D-SiNS-FET) biosensor was studied for the high-sensitivity detection of nucleic acids. Based on the mainstream Gate-All-Around (GAA) fenestration process, a three-dimensional stacked structure with an 8 nm cavity spacing was designed and prepared, allowing modification of probe molecules within the stacked cavities. Furthermore, the advantage of the three-dimensional space can realize the upper and lower complementary detection, which can overcome the Debye shielding effect and realize high-sensitivity Point of Care Testing (POCT) at high ionic strength. The experimental results show that the minimum detection limit for 12-base DNA (4 nM) at 1 × PBS is less than 10 zM, and at a high concentration of 1 µM DNA, the sensitivity of the 3D-SiNS-FET is approximately 10 times higher than that of the planar devices. This indicates that our device provides distinct advantages for detection, showing promise for future biosensor applications in clinical settings.

Catalytic Metal‐Gated Nano‐Sheet Field Effect Transistor and Nano‐Sheet Tunnel Field Effect Transistor Based Hydrogen Gas Sensor‐ A Design Perspective

AbstractIn this work, for the first time, the catalytic metal gate (CMG) based nanosheet Field Effect Transistor (NSFET) and nanosheet Tunnel Field Effect Transistor (NSTFET) are proposed for nano‐scale device dimensions, and the different design aspects of catalytic metal gate (CMG)‐based transduction for Hydrogen (H2) sensing are extensively investigated using numerical device simulation. The influence of applied biasing conditions and structural parameter specifications on the sensing performance of CMG‐NSFET and CMG‐NSTFET are methodically analyzed from device electrostatics and carrier transport mechanisms. Furthermore, the relative maximum sensitivity variations with H2‐partial pressure, ambient temperature, and the presence of ambient Oxygen are comprehensively studied. The study reveals that compared to CMG‐NSFET, the CMG‐NSTFET demonstrates a high immunity against bias and doping variations, with a notably higher (> 50%) sensitivity within low H2 partial pressures (10−15 – 10−10 Torr). Next, the sensing performance of CMG‐NSTFET is systematically optimized through a band‐gap and gate‐stack engineering approach, leading to a 180% to 650% sensitivity improvement from lower (10−15 Torr) to higher (10−5 Torr) range of H2 partial pressure. Finally, the performance of optimized CMG‐NSFET and CMG‐NSTFET are extensively benchmarked against other reported nanostructured CMG‐FET and TFET‐based H2 gas sensors, exhibiting a notably higher sensitivity in the proposed sensors.

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

Abstract In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off frequency (f T) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET.

Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

—In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field effect transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of the SHE and is dependent on the gate/drain voltage in different devices. Furthermore, the lattice maximum temperature-rise (ΔTmax), which directly leads to current degradation due to stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased gate/drain voltages. The ΔTmax increases at a decreasing rate with increasing VGS but increases approximately linearly as VDS increases. To investigate the origin of these behaviors, changes in thermal resistance (Rth) due to the shift in hot spot location and the redistribution of heat source under different applied voltages are also examined. The Rth decreases as VGS increases and slightly increases at a larger VDS. The Rth of NSFETs is generally larger than that of FinFETs, and the narrow-width NSFET (N-NSFET) has the largest Rth owing to the GAA structure and narrower sub-fin structure. Additionally, the heat flux ratio of the source thermal contact in N-NSFETs is smaller than that in FinFETs for different gate and sub-fin structures, resulting in reduced mean ΔT (ΔTmean) of N-NSFETs under a larger VGS, and therefore, leading to less current degradation. The study provides one effective design guide for GAA NSFETs optimizing their thermal characteristics in advanced nodes.

Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.

Design and Analysis of Nanosheet Field-Effect Transistor for High-Speed Switching Applications

Self-heating effects and short channel effects are unappealing side effects of multigate devices like gate-all-around nanowire-field-effect transistors (FETs) and fin FETs, limiting their performance and posing reliability difficulties. This paper proposes the use of the novel nanosheet FET (NsFET) for complementary metal-oxide semiconductor technology nodes that are changing. Design guidelines and basic measurements for the sub-nm node are displayed alongside a brief introduction to the roadmap to the sub-nm regime and electronic market. The device had an ION/IOFF ratio of more than 105, according to the proposed silicon-based NsFET. For low-power and high-switching applications, the results were verified and achieved quite well. When an NS width increases, although, the threshold voltage (Vth) tends to fall, resulting in a loss in subthreshold effectiveness. Furthermore, the proposed device performance, like subthreshold swing ION/IOFF, was studied with a conventional 2D FET. Hence, the proposed NsFET can be a frontrunner for ultra-low power and high-speed switching applications.

Optimization of vertically stacked nanosheet FET immune to self-heating

The self-heating effect (SHE) is one of the major challenges of ultra-scaled devices such as stacked nanosheet field effect transistor (SNSHFET) for sub 7 nm technology. The DC performance metrics of vertically SNSHFET are investigated and quantified against various geometrical parameters in the perspective of self-heating. Impact of self-heating is higher for larger gate and supply voltages. An average electron velocity reduction of 25 × 103 m/s and average electron mobility degradation of 242 cm2 V−1s−1 with SHE is observed for 5 nm thickness and 50 nm wider nanosheet. The increase in nanosheet width (WNSH) and thickness (tNSH), enhances device lattice temperature (TL) and other impediments. The results shows for the optimized device geometry, the SNSHFET exhibits better performance with immune to self-heating.

Enhancing UV-C Photoelectron Lifetimes for Avalanche-like Photocurrents in Carbon-Doped Bi3O4Cl Nanosheets.

Interlayer electric fields in two-dimensional (2D) materials create photoelectron protecting barriers useful to mitigate electron-hole recombination. However, tuning the interlayer electric field remains challenging. Here, carbon-doped Bi3O4Cl (C:Bi3O4Cl) nanosheets are synthesized using a gas phase protocol, and n-type carriers are acquired as confirmed by the transconductance polarity of nanosheet field effect transistors. Thin C:Bi3O4Cl nanosheets show excellent 266 nm photodetector figures of merit, and an avalanche-like photocurrent is demonstrated. Decaying behaviors of photoelectrons pumped by a 266 nm laser pulse (266 nm photoelectrons) are observed using transient absorption spectroscopy, and a significant 266 nm photoelectron lifetime quality in C:Bi3O4Cl is presented. Built C:Bi3O4Cl models suggest that the interlayer electric field can be boosted by two different carbon substitutions at the inner and outer bismuth sites. This work reports a facile approach to increase the interlayer electric field in Bi3O4Cl for future UV-C photodetector applications.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.