Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

Abstract

—In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field effect transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of the SHE and is dependent on the gate/drain voltage in different devices. Furthermore, the lattice maximum temperature-rise (ΔTmax), which directly leads to current degradation due to stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased gate/drain voltages. The ΔTmax increases at a decreasing rate with increasing VGS but increases approximately linearly as VDS increases. To investigate the origin of these behaviors, changes in thermal resistance (Rth) due to the shift in hot spot location and the redistribution of heat source under different applied voltages are also examined. The Rth decreases as VGS increases and slightly increases at a larger VDS. The Rth of NSFETs is generally larger than that of FinFETs, and the narrow-width NSFET (N-NSFET) has the largest Rth owing to the GAA structure and narrower sub-fin structure. Additionally, the heat flux ratio of the source thermal contact in N-NSFETs is smaller than that in FinFETs for different gate and sub-fin structures, resulting in reduced mean ΔT (ΔTmean) of N-NSFETs under a larger VGS, and therefore, leading to less current degradation. The study provides one effective design guide for GAA NSFETs optimizing their thermal characteristics in advanced nodes.