Nanosheet Field-effect Transistors Research Articles

Thermal, mechanical, and electrical properties of Si-stacked nanosheet transistors using machine learning interatomic potentials.

Thermal and mechanical properties play a key role in optimizing the performance of nanoelectronic devices. In this study, the lattice thermal conductivity (κL) and elastic constants of Si nanosheets at different sheet thicknesses were determined using recently developed machine learning interatomic potentials (MLIPs). A Si nanosheet with a minimum thickness of 10 atomic layers was used for model training to predict the properties of sheets with greater thicknesses. The training dataset was efficiently constructed using stochastic sampling of the potential energy surface (PES). Density functional theory (DFT) calculations were used to extract
the MLIP, which served as the basis for further analysis. The Moment Tensor Potential (MTP) method was used to obtain the MLIP in this study. The results showed that, at sub-6 nm sheet thickness, the thermal conductivity dropped to ∼ 7 % of its bulk value, whereas some stiffness tensor components dropped to ∼ 3 % of the bulk values. These findings contribute to the understanding of heat transport and mechanical behavior of ultrathin Si nanosheets, which is crucial for designing and optimizing nanoelectronic devices. The technological implications of the extracted parameters on nanosheet field-effect transistor (NS-FET) performance at advanced technology nodes were evaluated using TCAD device simulations.

A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Abstract IIn this paper, two substrate optimization approaches of triple stacked Nanosheet FET (SNSHFET), namely optimization of buried oxide and selective deposition of punch through stopper (PTS) substrate, have been examined and simulations have been carried out using Technology Computer-Aided (TCAD) software. A comprehensive study of leakage current and key electrical characteristics (I¬ON, VT, SS, DIBL) have also been extracted based on variation in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. GIDL current also increases with increased doping of the source and drain. Also, the impact of ultra-thin body substrate in SNSHFET is studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in Inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed at the channel-drain and gate-substrate overlap region for understanding the physical insights of leakage current in the SNSHFET. This work also answers the dependency of GIDL current on the gate and drain voltage supply respectively. In addition to that, how GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. The 3 nm-based SNSHFET is designed and its electrical and GIDL characteristics are compared with novel devices like Forksheet FET and Complementary FET.

Ohmic Contact Formation to β-Ga2O3 Nanosheet Transistors with Ar-Containing Plasma Treatment

Effective Ohmic contact between metals and their conductive channels is a crucial step in developing high-performance Ga2O3-based transistors. Distinct from bulk materials, excess thermal energy of the annealing process can destroy the low-dimensional material itself. Given the thermal budget concern, a feasible and moderate solution (i.e., Ar-containing plasma treatment) is proposed to achieve effective Ohmic junctions with (100) β-Ga2O3 nanosheets. The impact of four kinds of plasma treatments (i.e., gas mixtures SF6/Ar, SF6/O2/Ar, SF6/O2, and Ar) on (100) β-Ga2O3 crystals is comparatively studied by X-ray photoemission spectroscopy for the first time. With the optimal plasma pre-treatment (i.e., Ar plasma, 100 W, 60 s), the resulting β-Ga2O3 nanosheet field-effect transistors (FETs) show effective Ohmic contact (i.e., contact resistance RC of 104 Ω·mm) without any post-annealing, which leads to competitive device performance such as a high current on/off ratio (>107), a low subthreshold swing (SS, 249 mV/dec), and acceptable field-effect mobility (μeff, ~21.73 cm2 V−1 s−1). By using heavily doped β-Ga2O3 crystals (Ne, ~1020 cm−3) for Ar plasma treatments, the contact resistance RC can be further decreased to 5.2 Ω·mm. This work opens up new opportunities to enhance the Ohmic contact performance of low-dimensional Ga2O3-based transistors and can further benefit other oxide-based nanodevices.

Analysis of nano sheet field effect transistor based on performance under different temperature and doping concentrations for 12 nm device

This paper presents a simulation study on a 12 nm Gate-all-around n-type Metal Oxide Semiconductor (GAA-nMOSFET), investigating the effects of temperature variations and doping concentrations. The structure of the device has three fins, and the channel is surrounded by gate material to reduce the short channel effect (SCE) and electrostatic capacitance. Various parameters such as threshold voltage (Vth), Ion/Ioff ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS) are evaluated at different temperatures 250 K, 300 K, and 350 K, doping concentrations of 1016cm−3, 1017cm−3, and 1018cm−3, with a high voltage of 0.65V. At a temperature of 250 K, in comparison to the 1016cm−3 doping concentration attention, the Vth is observed to be 0.31V, while the Ion/Ioff ratio is measured at 0.33e−14. Moreover, the DIBL experiences a reduction of 25 %, whereas the SS increases by 76 %. Furthermore, when the temperature is raised to 300 K relative to the 1017cm−3 doping concentration, the Vth increases to 0.32 V, and the Ion/Ioff current ratio rises to 0.45e−14. Meanwhile, the DIBL experiences a decrease of 20 %, and the SS increases by 71 %. Finally, at a temperature of 350 K concerning 1018cm−3 doping concentration, the Vth is measured at 0.34 V, and the Ion/Ioff current ratio reaches 0.47e−14 Concurrently, the DIBL shows a decrease of 28 %, While the SS increases to 79 %. To reduce electrostatic capacitance and leakage current, the use of a high-k dielectric material in a GAA-nMOSFET device is investigated. Improved performance traits such as decreased SCE, low DIBL, and strong SS are displayed. Additionally, the connection between threshold voltage and doping concentration is investigated. The effect of temperature variations and doping concentration on many essential characteristics of 12 nm GAA-nMOSFET shows the potential benefits of the device's unique architecture and material. The conclusions are supported through circuit schematics, simulations, and experimental data in this article.

Design and performance analysis of double gate vertically stacked MoS2 nanosheet field effect transistor

In this work we report a vertically stacked nanosheet Field Effect Transistor (NSFET) in double gate configuration using transition metal dichalcogenide (TMD) based molybdenum disulphide (MoS2) as the conducting channel. The performance of the NSFET is analysed for number of channels, different channel thickness, different source/drain contacts. The performance of the device at different temperatures (T) also analysed. The proposed NSFET with three vertically stacked channels, exhibits a ON current (ION) of 30.6 μA μm−1, Subthreshold swing (SS) of 69 mV/dec and ON to OFF current ratio of more than 108 at Vds = 1V. Further the ION can be improved with multi-layer channel thickness. The performance of the vertically stacked MoS2 NSFET in junction less (JL) and inversion mode (IM) is compared, it is concluded from the simulations that JL vertically stacked MoS2 NSFET more immune to short channel effects such as threshold voltage (Vth) roll-off and drain induced barrier lowering (DIBL).

Noise coupling reduction using temperature enhanced device for future integrated circuit integration applications

<p>Information technology-to-internet of things may have succeeded because of fast silicon chip capability expansion. Moore's law, which reduces device size, boosted integrated circuit (IC) performance. Delay rises with highdensity connection parasitic capacitance. Interconnect delays have surpassed transistor delays and slowed progress. An alternative is required now to reduce connection latency. The third dimension is used in popular 3D IC technology IC technology requires through silicon via (TSV) for signal integrity and heat mitigation. Noise coupling hinders electrical communication between signal-carrying TSVs (aggressive TSVs) and ground TSVs (victim TSVs), a 3D IC bottleneck. TSVs must be dielectrically insulated from Si substrates to avoid electrical signal interference. Additionally, first-order modelling will confirm the suggestions. This article proposes using the nanosheet field effect transistor (NSFET) to overcome 3D IC noise coupling and complementary metal oxide semiconductor (CMOS) technology nodes. After discussing the electronic industry and sub nm, several basic metrics and criteria for developing electronic components are presented. The first technique uses Perylene-N's exceptional noise-cancelling characteristics. Second technique uses electrical TSV (ETSV), thermal TSV (TTSV), and heat source models to measure noise coupling on numerous ICs. The third proposes many noise-reducing materials. The suggested structures outperform traditional approaches.</p>

A Comprehensive Analysis of Nanosheet Field-Effect Transistor: Recent Advances and Comparative Study

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability.

Accurate Evaluation of Electro-Thermal Performance in Silicon Nanosheet Field-Effect Transistors with Schemes for Controlling Parasitic Bottom Transistors.

The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.

Core-insulator embedded nanosheet field-effect transistor for suppressing device-to-device variations

Nanosheet field-effect transistors (NSFETs) have attracted considerable attention for their potential to achieve improved performance and energy efficiency compared to traditional FinFETs. Here, we present a comprehensive investigation of core-insulator-embedded nanosheet field-effect transistors (C-NSFETs), focusing on their improved performance and device-to-device (D2D) variability compared to conventional NSFETs through three-dimensional device simulations. The C-NSFETs exhibit enhanced direct-current (DC) performance, characterized by a steeper subthreshold slope and reduced off-current, indicating better gate electrostatic controllability. Furthermore, the structural design of C-NSFETs enables to demonstrate a notable resilience against D2D variations in nanosheet thickness and doping concentration. In addition, we investigate the effects of interface traps in C-NSFETs, emphasizing the importance of thermal oxidation processes in the formation of core-insulating layers to maintain optimal device performance.

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers.

In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

Interaction of Negative Bias Instability and Self-Heating Effect on Threshold Voltage and SRAM (Static Random-Access Memory) Stability of Nanosheet Field-Effect Transistors.

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect.

Investigation of spacer-engineered stacked nanosheet tunnel FET with varying design attributes

The stacked nanosheet field-effect transistors (SNS-FETs) are potential contenders for sub-7 nm technology. Device miniaturization leads to a larger off-state current and a higher subthreshold slope in SNS-FETs. Unlike SNS-FETs, the stacked nanosheet tunnelling field effect transistors (SNS-TFETs) function as switches in integrated circuits, featuring high performance and low power consumption. The endeavour aims to investigate how each design parameter optimises the switching characteristics of the SNS-TFET device. This paper examines various design attributes, such as different dielectric spacer materials, nanosheet width (NW), nanosheet thickness (NT), source doping, drain doping, etc. The Cogenda Visual TCAD serves as a tool for conducting device simulations. According to the simulation study, the use of a high-k hafnium dioxide (HfO2) spacer produces a higher switching ratio ( 7.28×1011 ) and a lower subthreshold swing (20.303 mV/decade). Using either low-k or no spacers reduces the overall gate capacitance and unit frequency gain compared to high-k spacers. Upscaling the nanosheet width (10 to 50 nm) enhances the switching ratio by 1.11×101 and transconductance by 61.92%. Downscaling the nanosheet thickness (6 to 4 nm) at the optimized nanosheet width (50 nm) improves the switching ratio by 1.88. Increasing the gate length from 8 to 16 nm reduces the leakage current by 2.34×10−2 A and improves the switching ratio by 2.90×101. An increase in the source doping level from 1×1020 to 5×1020 cm−3 results in a 1.07×102 decrease in the switching ratio and a 2.48-fold increase in the subthreshold swing. Furthermore, the findings indicate that drain doping is crucial in determining ambipolar current. In SNS-TFET, ambipolar current reduces significantly when drain doping is 1×1017 cm−3. Thus, the proposed work addresses the limitations of scaling and optimised design parameter characteristics for low-power nanoscale circuits.

Ultrasensitive 3D Stacked Silicon Nanosheet Field-Effect Transistor Biosensor with Overcoming Debye Shielding Effect for Detection of DNA.

Silicon nanowire field effect (SiNW-FET) biosensors have been successfully used in the detection of nucleic acids, proteins and other molecules owing to their advantages of ultra-high sensitivity, high specificity, and label-free and immediate response. However, the presence of the Debye shielding effect in semiconductor devices severely reduces their detection sensitivity. In this paper, a three-dimensional stacked silicon nanosheet FET (3D-SiNS-FET) biosensor was studied for the high-sensitivity detection of nucleic acids. Based on the mainstream Gate-All-Around (GAA) fenestration process, a three-dimensional stacked structure with an 8 nm cavity spacing was designed and prepared, allowing modification of probe molecules within the stacked cavities. Furthermore, the advantage of the three-dimensional space can realize the upper and lower complementary detection, which can overcome the Debye shielding effect and realize high-sensitivity Point of Care Testing (POCT) at high ionic strength. The experimental results show that the minimum detection limit for 12-base DNA (4 nM) at 1 × PBS is less than 10 zM, and at a high concentration of 1 µM DNA, the sensitivity of the 3D-SiNS-FET is approximately 10 times higher than that of the planar devices. This indicates that our device provides distinct advantages for detection, showing promise for future biosensor applications in clinical settings.

Catalytic Metal‐Gated Nano‐Sheet Field Effect Transistor and Nano‐Sheet Tunnel Field Effect Transistor Based Hydrogen Gas Sensor‐ A Design Perspective

AbstractIn this work, for the first time, the catalytic metal gate (CMG) based nanosheet Field Effect Transistor (NSFET) and nanosheet Tunnel Field Effect Transistor (NSTFET) are proposed for nano‐scale device dimensions, and the different design aspects of catalytic metal gate (CMG)‐based transduction for Hydrogen (H2) sensing are extensively investigated using numerical device simulation. The influence of applied biasing conditions and structural parameter specifications on the sensing performance of CMG‐NSFET and CMG‐NSTFET are methodically analyzed from device electrostatics and carrier transport mechanisms. Furthermore, the relative maximum sensitivity variations with H2‐partial pressure, ambient temperature, and the presence of ambient Oxygen are comprehensively studied. The study reveals that compared to CMG‐NSFET, the CMG‐NSTFET demonstrates a high immunity against bias and doping variations, with a notably higher (> 50%) sensitivity within low H2 partial pressures (10−15 – 10−10 Torr). Next, the sensing performance of CMG‐NSTFET is systematically optimized through a band‐gap and gate‐stack engineering approach, leading to a 180% to 650% sensitivity improvement from lower (10−15 Torr) to higher (10−5 Torr) range of H2 partial pressure. Finally, the performance of optimized CMG‐NSFET and CMG‐NSTFET are extensively benchmarked against other reported nanostructured CMG‐FET and TFET‐based H2 gas sensors, exhibiting a notably higher sensitivity in the proposed sensors.

Multiphysics Simulation of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in Gate-All-Around Nanosheet Field Effect Transistors

Multiphysics Simulation of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in Gate-All-Around Nanosheet Field Effect Transistors

Parasitic Capacitance Model for Stacked Gate-All-Around Nanosheet FETs

Gate-all-around (GAA) nanosheet field-effect transistors (NSFETs) are hailed as the most promising architecture for the incessant scaling of MOSFETs to the sub-5-nm technology node and beyond. Although the GAA structure and the ultra-thin channel lead to a significantly improved static performance owing to the enhanced electrostatic integrity and higher immunity against the short-channel effects, the vertical stacking and the inherent 3-D-geometry result in a large parasitic capacitance and may degrade the dynamic performance. Therefore, it becomes imperative to analyze the parasitic capacitance components in GAA NSFETs and provide design guidelines for optimizing the dynamic performance. To this end, in this work, we have formulated an analytical model for the total gate parasitic capacitance in GAA NSFETs, considering contributions from different parasitic capacitance components. Furthermore, we have also investigated the variation in parasitic capacitance components with the structural parameters for design optimization of GAA NSFETs from a dynamic performance perspective. The result of the developed model is in good agreement with TCAD simulation result indicating the efficacy of the analytical model.

Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors

A novel and practicable partial punch-through-stopper (p-PTS) scheme beneath the gate area is proposed for the substrate leakage current suppression in the gate-all-around (GAA) nanosheet field-effect transistors (NSFETs). Thanks to the weakened electric field and widened tunneling length caused by the lightly doped substrate under the drain region, this p-PTS scheme can not only achieve a low PT current comparable to the conventional full-PTS (f-PTS) scheme, but also substantially reduce the BTBT current of drain–substrate junction by about two orders of magnitude. Moreover, the key parameters of the p-PTS scheme, such as p-PTS doping concentration (Np-PTS), thickness (Tp-PTS) and width (Wp-PTS), are systematically optimized and analyzed. As a result, compared to the conventional f-PTS scheme, p-PTS scheme exhibits a larger process window and better immunity of leakage current to process variations. The above results indicate that the proposed p-PTS scheme is one of the most promising methods for suppressing substrate leakage current in NSFET.

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

Abstract In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off frequency (f T) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET.

Investigation on dependency of thermal characteristics on gate/drain bias voltages in stacked nanosheet transistors

—In this paper, the gate/drain voltage-dependent self-heating effect (SHE) in gate-all-around (GAA) nanosheet field effect transistors (NSFETs) and FinFETs is investigated by 3-D TCAD simulation. The drain current decreases because of the SHE and is dependent on the gate/drain voltage in different devices. Furthermore, the lattice maximum temperature-rise (ΔTmax), which directly leads to current degradation due to stronger carrier mobility scattering under higher temperature, exhibits complex trends with increased gate/drain voltages. The ΔTmax increases at a decreasing rate with increasing VGS but increases approximately linearly as VDS increases. To investigate the origin of these behaviors, changes in thermal resistance (Rth) due to the shift in hot spot location and the redistribution of heat source under different applied voltages are also examined. The Rth decreases as VGS increases and slightly increases at a larger VDS. The Rth of NSFETs is generally larger than that of FinFETs, and the narrow-width NSFET (N-NSFET) has the largest Rth owing to the GAA structure and narrower sub-fin structure. Additionally, the heat flux ratio of the source thermal contact in N-NSFETs is smaller than that in FinFETs for different gate and sub-fin structures, resulting in reduced mean ΔT (ΔTmean) of N-NSFETs under a larger VGS, and therefore, leading to less current degradation. The study provides one effective design guide for GAA NSFETs optimizing their thermal characteristics in advanced nodes.

Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

This work presents an experimental evaluation of n-type, gate-all-around (GAA), vertically stacked nanosheet field effect transistors (NSFETs) operating in a temperature (T) range from 473 K down to 173 K and focusing on their use for analog applications. Devices with gate lengths (Lgate) of 28 nm to 200 nm were analyzed. Besides exhibiting a slight short channel effect, the shorter transistors show a good performance in terms of analog application, presenting at 173 K an intrinsic voltage gain (AV) of 30 dB and unit gain frequency (fT) of 185 GHz. This is also seen in two figures of merit that characterize the transistor performance for analog circuit design: the transistor efficiency (gm/IDS) and the gain frequency product (AV*fT). The optimum region of operation was demonstrated to be at strong inversion by the trade-off between gm/IDS and fT, where in this region Lgate = 28 nm presents a gain frequency product of ∼ 5,5THz at T = 173 K. At lower temperature, as expected, it is confirmed that the carrier mobility and the subthreshold swing (SS) improve while the threshold voltage (VT) increases.