Nanoscale Double-gate MOSFETs Research Articles

A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs

A Generalized Analytical Approach to Model the Gate Tunneling Current in Nanoscale Double Gate MOSFETs

Design and analysis of ultra-thin dielectric film embedded nanoscale double-gate MOSFETs for boosting logic performance

This paper presents a systematic study on the performance of double gate (DG)-MOSFETs with an ultrathin embedded dielectric film (DF) at the center of the channel from the source to drain of the device. The numerical simulation results show that for k ≤ 12, the value of ION/IOFF of a 20-nm DF-DG-MOSFET increases with increasing value of DF thickness t reaching a maximum value of about 107 for dielectric constant k = 1, and t = 5 nm whereas, tends to decrease for k > 12. Also, the 20 nm DF-DG-MOSFET with (k = 1, t = 5 nm) shows the lowest subthreshold swing SS of 79 mV/decade and drain induced barrier lowering DIBL of 109 mV/V. However, the intrinsic delay of DF-DG-MOSFET increases with increasing t for k ≤ 12, whereas, decreases as both t and k increase for k > 12 reaching a value of 0.5 ps for (k = 80, t = 5 nm) compared to 0.8 ps for an identical conventional DG-MOSFET. This study, clearly, shows that the performance of DG-MOSFETs can be optimized by wise choice of t and k of an embedded DF and provides guidelines for the design of high performance and low power nanoscale logic devices.

Performance evaluation of nanoscale halo dual-material double gate SiGe MOSFET using 2-D numerical simulation

Abstract The recent interest in SiGe for multigate MOSFET design has demonstrated the possibility of alleviating many parasitic effects dominating at nanoscale regime. In the presented work, we focus on the performance analysis of nanoscale double gate MOSFET with a SiGe channel. The influence of introducing some structural modifications at the level of the device is shown namely the halo aspect, high-k gate stack and the dual metal gate technologies. The numerical experiments carried out using ATLAS-2D simulator confirm such enhancement with respect to a pure Si based channel device in terms of transconductance and output conductance. It is worth mentioning that other channel and gate engineering techniques deserve to be investigated in the context of SiGe multigate MOSFETs with the hope of further performance improvement

Performance analysis of nanoscale double gate strained silicon MOSFET with high k dielectric layers

This study presents a theoretical model to describe the combined characteristics of strained silicon nanoscale double gate MOSFET along with high k dielectric layer. Although a well- tempered MOSFET with strong gate electrostatics can be devised using high k gate material, lower conduction band offset (CBO) over silicon results in leakage and subsequent static power dissipation. The study shows that this effect can reduce the Ion/Ioff ratio to 2 × 102 with 2 nm thick TiO2 dielectric layer (k = 60) along with mobility degradation. Incorporating the effects of strained silicon and high k dielectrics in MOSFETs exhibits bandstructure alteration and increase in CBO. This inhibits carrier tunnelling causing leakage with restoration of Ion/Ioff ratio to 4.5 × 106. The mobility can also be improved along with the maintenance of effective gate electrostatics. Thus the study illustrates the possibility of designing the nanoscale MOS devices with all the essential characteristics without trade-off over other performance parameters.

Asymmetric underlap spacer layer enabled nanoscale double gate MOSFETs for design of ultra-wideband cascode amplifiers

Using extensive numerical analysis we investigate effects of asymmetric sidewall spacers on various device parameters of 20-nm double gate MOSFETs associated with analog/RF applications. Our studies show that the device with underlap drain-side spacer length LED of 10 nm and source-side spacer length LES of 5 nm shows improvement in terms of the peak value of transconductance efficiency, voltage gain Av, unity-gain cut-off frequency fT and maximum frequency of oscillations fMAX by 8.6%, 51.7%, 5% and 10.3%, respectively compared to the symmetric 5 nm underlap spacer device with HfO2 spacer of dielectric constant k = 22. Additionally, a higher spacer dielectric constant increases the peak Av while decreasing both peak fT and fMAX. The detailed physical insight is exploited to design a cascode amplifier which yields an ultra-wide gain bandwidth of 2.48 THz at LED = 10 nm with a SiO2 spacer.

Design and Simulation of Nanoscale Double Gate MOSFET using high K Material and Ballistic Transport Method

The Phenomenal scaling of MOSFET helps in sustaining of Moore’s law and also helped in improving the performance. As per the 2009 ITRS projection document the channel length will go down to 12nm approximately by 2020 and moving beyond the 50nm technology conventional MOSFET technology needs advancement to overcome the restrictions imposed by fundamental Physics [1] such as tunnelling of charge carriers through gate oxide, increased leakage current. Reduction in leakage current and short channel effects can be achieved using high K dielectric material. Double gate MOSFET is another possible solution as multiple gates devices improves the circuit performance like improvement in the short channel effects because of better charge control, faster circuit speed because of increased current. Improvement of short channel effects in Double gate MOSFET allows additional gate length scaling.

Erratum: A Compact Scattering Model for the Nanoscale Double-Gate MOSFET [Mar 02 481-489

Corrections to formulas and equations for the paper A Compact Scattering Model for the Nanoscale Double-Gate MOSFET (Rahman, A. and Lundstrom, M.S.; IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 481–489, Mar. 2002) )are presented.

A new technique to control floating body effect in nano-scale double-gate MOSFET

This paper proposes a novel structure of Double Gate (DG) MOSFET to control the impacts of floating body effect. Floating body effect increases hole concentration in the channel region due to the impact ionization. In this novel structure which is named as SiGe Region in DG-MOSFET (SR-DG) two spacers are considered in both sides of gate region and a SiGe zone is incorporated in gate–source spacer. The SiGe region with lower band gap than silicon collects the excess hole in the channel. Our simulation with two dimensional ATLAS simulator shows that the proposed SR-DG improves the performance of DG-MOSFET in terms of threshold voltage, breakdown voltage and electric field. Also, the impacts of parasitic bipolar junction transistor (BJT) are controlled significantly.

Modeling the Channel Charge and Potential in Quasi-Ballistic Nanoscale Double-Gate MOSFETs

In this paper, we present an analytical semiempirical model of the profile of the channel charge and potential in quasi-ballistic double-gate (DG) MOSFETs. The charge model is based on the premise of separating the charge density in the quasi-ballistic channel into two hypothetical components: 1) exclusively ballistic (collision-free) and 2) collision-dominated components, which are governed by the same electrostatics. These components are related to each other through a ballisticity parameter whose values lie between 0 and 1. Varying the value of this parameter allows us to model the charge profile continuously between diffusive and purely ballistic devices. Using the proposed charge model and the DG MOSFET electrostatics, an analytical expression for the channel potential is derived which, like the charge model, is continuous between the diffusive and ballistic regimes.

Analytical temperature dependent model for nanoscale double-gate MOSFETs reproducing advanced transport models

In this paper we extend our compact model for nanoscale double-gate (DG) MOSFETs which considers a hydrodynamic transport model to include the effect of the temperature dependence. Temperature dependence equations are incorporated to the expressions of the mobility and saturation velocity. For model validation we have considered a symmetric 22nm double-gate MOSFET template device optimized for low-stand-by-power applications. Comparison between the numerical 2D Monte Carlo (MC) simulations and the compact model shows a good degree of agreement.

Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor

In this paper, a compact modeling of lightly doped nanoscale Double Gate (DG) MOSFET transistor is presented. In the first time, a DG MOSFET transistor with long channel is considered. In this case, by using 1-D Poissons equation and applying the Gauss law at the interface of Silicone/Oxide, the static behavior of the long channel DG MOSFET can be observed by simple relationships between charges-voltages and charges-drain current. In second time, the dynamic behavior of the device is described through the intrinsic trans-capacitances. The present results (obtained using MATLAB) are validated by comparing them with those obtained using commercial software (Silvaco Atlas-TCAD).

Bias optimization of 2.4 GHz double gate MOSFET RF mixer

The optimum biasing points and structural design parameters for novel nano-scale double gate MOSFET (DG-MOSFET) radio frequency mixers are investigated at 2.4 GHz. Our objective is to analyze and identify the correlation of the conversion gain of the mixer circuit with the signal amplitude of the local oscillator (LO) as well as different device parameters, such as the gate length (L gate ), doping concentration (N A ) and body thickness (t Si ), thus minimizing signal loss and power consumption and increasing stability. The most important figure of merit is found to be the LO DC bias that determines the level of non-linearity in the transconductance response. Furthermore, we observe that in properly designed DG-MOSFETs $$(\hbox{L}_{gate} \ge 3t_{Si}),\; \hbox{L}_{gate}$$ ( L g a t e ? 3 t S i ) , L g a t e and N A have limited impact on the conversion gain of the mixer, while t Si has a more significant role to play. Although the mixing performance of DG-MOSFETs is ultimately limited by the short channel effects perpetrated by any given structural constraint, an optimum body thickness t Si exists in each case to maximize the conversion gain. Thus, we illustrate how 2D and quantum-corrected simulations can identify the optimum body thickness and optimum bias conditions in such compact nano-scale mixers.

ANFIS-based approach to studying subthreshold behavior including the traps effect for nanoscale thin-film DG MOSFETs

A fuzzy framework based on an adaptive network fuzzy inference system (ANFIS) is proposed to evaluate the relative degradation of the basic subthreshold parameters due to hot-carrier effects for nanoscale thin-film double-gate (DG) MOSFETs. The effect of the channel length and thickness on the resulting degradation is addressed, and 2-D numerical simulations are used for the elaboration of the training database. Several membership function shapes are developed, and the best one in terms of accuracy is selected. The predicted results agree well with the 2-D numerical simulations and can be efficiently used to investigate the impact of the interface fixed charges and quantum confinement on nanoscale DG MOSFET subthreshold behavior. Therefore, the proposed ANFIS-based approach offers a simple and accurate technique to study nanoscale devices, including the hot-carrier and quantum effects.

Fuzzy-logic-based approach to study the electrons mobility in nanoscale Double Gate MOSFETs

The Double Gate silicon (DG) MOSFET with extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the electron mobility distribution throughout the channel must be accurately determined under the application of drain and gate voltages. However, the modeling of the transport behavior for the nanoscale structures requires the use of overkill methods and models in terms of complexity and computation time (self-consistent, quantum computations,..). Therefore, new methods and techniques are required to overcome these constraints. In this work, a new approach based on the fuzzy logic computation is proposed to model the electron mobility behavior for nanoscale DG MOSFETs. The proposed approach can be implemented into devices simulator to study the nanoscale CMOS-based circuits.

Simulation of a double-gate MOSFET by a non-parabolic energy-transport subband model for semiconductors based on the maximum entropy principle

A nanoscale double-gate MOSFET is simulated with an energy-transport subband model for semiconductors including the effects of non-parabolicity by means of the Kane dispersion relation. The closure relations are derived on the basis of the maximum entropy principle and all the relevant scattering mechanisms of electrons with acoustic and non polar optical phonons are taken into account. The model is shown to form a system of nonlinear parabolic partial differential equations.The results of the simulations validate the robustness of the numerical scheme and the accuracy of the model. In particular, the importance of taking into account the non-parabolicity is assessed, since a relevant difference in the currents is obtained in comparison with the parabolic band case.

Accurate modeling of the influence of back gate bias and interface roughness on the threshold voltage of nanoscale DG MOSFETs

An accurate 2-D analytical model regarding the influence of back gate bias Vbg on the threshold voltage of double gate (DG) MOSFETs for a wide range of geometric dimensions and gate materials is presented. The threshold voltage Vt and its variation have been determined with different geometric dimensions taking into account several effects such as quantum mechanical effects and the surface roughness effect for various back gate bias conditions. Our theoretical calculations rely on the solution of 2-D Poisson’s equation while numerical simulation results are obtained from the numerical device simulator ATLAS. The shift in Vt due to quantum effects and the surface roughness-induced effect has been calculated by employing the accurate value of ground state energy computed using variational approach for a finite rectangular quantum well as exists in a real DG MOS structure. Our investigations show that Vt increases with increasing negative Vbg and exhibits significant enhancement due to quantum effects and the surface roughness effect particularly for channel thickness below 5nm. The margin of accuracy has been verified by comparing our analytical and simulation results with reported simulation and experimental data for various devices.

A fuzzy-logic-based approach to accurate modeling of a double gate MOSFET for nanoelectronic circuit design

The double gate (DG) silicon MOSFET with an extremely short-channel length has the appropriate features to constitute the devices for nanoscale circuit design. To develop a physical model for extremely scaled DG MOSFETs, the drain current in the channel must be accurately determined under the application of drain and gate voltages. However, modeling the transport mechanism for the nanoscale structures requires the use of overkill methods and models in terms of their complexity and computation time (self-consistent, quantum computations, …). Therefore, new methods and techniques are required to overcome these constraints. In this paper, a new approach based on the fuzzy logic computation is proposed to investigate nanoscale DG MOSFETs. The proposed approach has been implemented in a device simulator to show the impact of the proposed approach on the nanoelectronic circuit design. The approach is general and thus is suitable for any type of nanoscale structure investigation problems in the nanotechnology industry.

Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model

This paper presents a compact gate leakage current partitioning model for nanoscale Double Gate (DG) MOSFETs, using analytical models of the direct tunneling gate leakage current. Gate leakage current becomes important and an essential aspect of MOSFET modeling as the gate oxide thickness is scaled down to 1nm and below in advanced CMOS processes. We considered an ideal interface (ideal case without an interfacial layer) and two layers high k dielectric materials as gate insulators. In the case of two layers, a thin layer of SiO2 as an interfacial layer is considered. The results of the gate current partitioning components into drain and source show good agreement with 2D TCAD numerical device simulation (Silvaco Atlas).

Analysis of temperature and wave function penetration effects in nanoscale double-gate MOSFETs

Wave function penetration has significant impact on nanoscale devices having ultrathin gate oxide. Although wave function penetration effects on ballistic drain current and capacitance-voltage characteristics in nanoscale devices have been reported in literature, to the best of the authors’ knowledge, effects of temperature on drain current incorporating with and without wave function penetration are yet to be studied. In this work, the impacts of temperature, gate dielectric and film thickness in wave function penetration on ballistic drain current of nanoscale double-gate (DG) MOSFETs are presented. The effects are observed using two-dimensional self-consistent solution of Schrödinger and Poisson equations. It has been obtained that temperature effect on drain current is greatly dependent on silicon surface orientation. Drain current of DG MOSFETs fabricated on $$\langle110\rangle$$ surface is more sensitive to temperature compared to $$\langle001\rangle$$ surface. This has been obtained for both the cases with and without incorporating wave function penetration in silicon–gate oxide interface. Electrostatics behind this phenomenon has been explained from the transmission probability of electrons from source to drain which is largely influenced by temperature on $$\langle110\rangle$$ surface compared to $$\langle001\rangle.$$ Moreover, the transmission coefficient is significantly affected by wave function penetration in $$\langle110\rangle \hbox{ than }\langle001\rangle$$ surface. Both these demonstrate greater sensitivity of temperature and wave function penetration in $$\langle110\rangle$$ silicon surface orientation compared to $$\langle001\rangle.$$ Furthermore, gate dielectric with lower conduction band offset and device scaling with thin channel thickness tend to exhibit greater impact of wave function penetration.

Numerical simulation of a double-gate MOSFET with a subband model for semiconductors based on the maximum entropy principle

A nanoscale double-gate MOSFET is simulated with an energy-transport subband model for semiconductors formulated starting from the moment system derived from the Schrodinger–Poisson–Boltzmann equations. The system is closed on the basis of the maximum entropy principle and includes scattering of electrons with acoustic and non-polar optical phonons. The proposed expression of the entropy combines quantum effects and semiclassical transport by weighting the contribution of each subband with the square modulus of the envelope functions arising from the Schrodinger–Poisson subsystem. The simulations show that the model is able to capture the relevant confining and transport features and assess the robustness of the numerical scheme.