Nanoribbon Field-effect Transistors Research Articles

Design of a Low-Power Short-Channel Electrostatically Doped Silicene Nanoribbon FET

In this article, the transfer and output characteristics of an electrostatically doped (ED) 4-armchair silicene nanoribbon (4-ASiNR) field-effect transistor (FET) with three gates are investigated. The numerical simulations are carried out based on the self-consistent solution of the Poisson and Schrodinger equations within the nonequilibrium Green’s function (NEGF) formalism, implemented in the NanoTCAD ViDES simulator. Results show that ED SiNR-FET has better characteristics than chemically doped (CD) SiNR-FET. Additionally, ED-device is inherently free of negative impacts of impurities on the transistor’s performance. The ED SiNR-FET functionality is analyzed using different channel lengths, introducing the extended channel ED-device (ECED) with an improved ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $3.8\times 10^{5}$ and a significant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of 4.6 mA/ $\boldsymbol \mu \text{m}$ . A 15 nm ECED SiNR-FET with an 8 nm channel is studied under different temperatures and supply voltages. Based on the results, low-power (LP) and high-performance (HP) applications are suggested for the ECED-device, with the minimum subthreshold swing of 64 mV / dec and the maximum transconductance of $63~\boldsymbol \mu \text{S}$ , respectively.

Graphene Nanoribbon FET Compact Model on the Basis of ANN Configuration Applicable in Different Spice Levels

The artificial neural networks (ANNs) are widely utilized as a powerful approximator for a vast number of complicated nonlinear functions in many fields in different domains. Multi-layer perceptron (MLP) as a unique strategy in this work has been highlighted making an analytical drain current prediction of graphene nanoribbon field-effect transistor (GNRFET) simple and efficient having a linear dependence on the fundamental variables. The MLP structure in this work is configured with three hidden layers and 5-dimensional inputs giving the best result after performing different experiments. Target output as the key parameter is actually the numerically calculated drain current by the Non-Equilibrium Green Function (NEGF) method which is commonly used for the simulation of nanoscale devices. The critical parameters in the cases of gate oxide thickness, gate length, number of carbon atoms across the channel, gate voltage, and drain voltage are selected as the dimensions of the input vector impacting the obtained drain current by the ANN. The comprehensive comparison between the NEGF approach and the proposed ANN-based model revealed an excellent match and correlation between them. As a result, this model can be taken into consideration as a suitable tool in the different spice levels owing to the saving the running time and also increase in the efficiency of nanoscale circuits based on the GNRFET structure.

DC performance analysis of III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon FET circuits with quantum mechanical effects

In this article, the electrical behavior of laterally grown novel short-channel III–V/Si heterostructure double gate triple material PiN tunneling graphene nanoribbon field effect transistor (DG-TM-PiN-TGNFET) has been studied based on their quantum mechanical effect (QME). Firstly, by varying the device process parameters of the novel TFET structure, the DC parameter responses viz. threshold voltage, electric field and surface potential are investigated. Further these responses are analyzed by considering the QME for better device performance. Two-dimensional numerical device simulator (SILVACO TCAD) tool is used for simulating the quantum and semi-classical models. The simulation work has been validated by extensive analytical modeling, that reflected in our accurate graphical representations. Finally, to investigate the QME effect in circuit level applications, an TFET inverter circuit has been designed and its DC performance viz. power dissipation and propagation delay analysis is performed.

Narrower Nanoribbon Biosensors Fabricated by Chemical Lift-off Lithography Show Higher Sensitivity.

Wafer-scale nanoribbon field-effect transistor (FET) biosensors fabricated by straightforward top-down processes are demonstrated as sensing platforms with high sensitivity to a broad range of biological targets. Nanoribbons with 350 nm widths (700 nm pitch) were patterned by chemical lift-off lithography using high-throughput, low-cost commercial digital versatile disks (DVDs) as masters. Lift-off lithography was also used to pattern ribbons with 2 μm or 20 μm widths (4 or 40 μm pitches, respectively) using masters fabricated by photolithography. For all widths, highly aligned, quasi-one-dimensional (1D) ribbon arrays were produced over centimeter length scales by sputtering to deposit 20 nm thin-film In2O3 as the semiconductor. Compared to 20 μm wide microribbons, FET sensors with 350 nm wide nanoribbons showed higher sensitivity to pH over a broad range (pH 5 to 10). Nanoribbon FETs functionalized with a serotonin-specific aptamer demonstrated larger responses to equimolar serotonin in high ionic strength buffer than those of microribbon FETs. Field-effect transistors with 350 nm wide nanoribbons functionalized with single-stranded DNA showed greater sensitivity to detecting complementary DNA hybridization vs 20 μm microribbon FETs. In all, we illustrate facile fabrication and use of large-area, uniform In2O3 nanoribbon FETs for ion, small-molecule, and oligonucleotide detection where higher surface-to-volume ratios translate to better detection sensitivities.

Influence of Device Parameters on Performance of Ultra-Scaled Graphene Nanoribbon Field Effect Transistor

Recent advances in graphene nanoribbon (GNR) field-effect transistors (FETs), with finite band-gap, have shown great promise for their use in ultra-scaled, low power and high speed device applications. Here, we use quantum mechanical simulations, based on non-equilibrium Green’s function (NEGF), to study the electrical characteristics of a sub-10 nm gate length GNRFET with double gate structure. Tight-binding approximation is used to extract the energy bands of GNR and the results are validated with density functional theory (DFT) calculations. Key electrical parameters are computed for different dielectric material, source/drain doping and temperature combining the channel length scaling beyond 10 nm to study performance variation. Results reveal that change in source/drain doping shows significant impact on performance for shorter channel, while the opposite tendency is observed for dielectric constant (k) variation. GNRFET showed robustness against temperature variation compared to conventional Si devices. Finally, the results were benchmarked against the performance metrics of high performance and low power CMOS devices in the 5-nm technology node. A significant rise in leakage current beyond the LP requirement was observed for gate lengths below 5 nm. Results obtained from this study can provide useful insights in the design and implementation of next generation GNRFETs.

High Speed Terahertz Devices via Emerging Hybrid GNRFET/Josephson Junction Technologies

An approach to merge superconducting Josephson junction (JJ) devices with nanoscale Graphene devices in order to achieve high gain-bandwidth-product on the order of THz is proposed. While JJ-based devices have existed since nearly 1962, interfacing or interacting with them with standard electrical systems has been a challenge for several reasons, including operating temperature, switching speed, and low-signal sensitivity. In this article, we investigated the possibility of utilizing JJ's so-called ac effect in order to generate high frequency signals that can be accommodated by high speed nanoscale devices. Graphene nanoribbon field effect transistors (GNRFET) have been emphasized for their very high frequency operation that is appropriate to accommodate the very high switching speed of the JJ devices. The article is based on the ac JJ effect with generating a sinusoidal current whose frequency directly scales with voltage. For a single-stage GNRFET CS amplifier, a gain of 35.7 dB with a bandwidth of 217 GHz was achieved, while 10.8 dB with a unitary gain of 2.5 THz was also accomplished. This article details the design and interface of the JJ with GNRFET devices, targeting high frequency signal generation on the order of hundreds of GHz to THz, with the purpose of providing a foundation on top of which further developments can be made, especially in the areas of communications, medical devices, instrumentation and measurement devices, high-speed imaging, subinfrared antenna arrays, and computer architecture and hardware, by providing a system, which can respond to speeds on the order of fifty to one hundred times faster than current commercial computer equipment or signal generation/processing.

New Approach for Designing and Optimally Selecting the Parameters of Graphene nano-ribbon Transistors in the Presence of Process Variation

GNRFET Graphene Nano-Ribbon Field-Effect Transistor is sensitive to geometric parameters. Therefore, changing parameters circuit characteristics can be improved or degraded. In this study, we propose a new approach to optimizing the GNRFETs. The effect of geometric and process parameters such as chirality, channel length, width, line edge roughness, oxide thickness, and doping on characteristics of an inverter gate is investigated based on GNRFET. Analysis of power consumption, delay, PDP, and SNM results indicate that GNRFETs adjustable parameters can significantly affect circuit performance. It is shown that SNM increases by changing channel length and width. Moreover, by reducing the channel length from 20 nm to 10 nm, delay for chirality (6,0) decreases by 50%, and delay for chirality (10,0) decreases by 53%. By increasing the Line Edge Roughness by 20%, power consumption for chirality (10,0) and chirality (6,0) increases by 18% and exponentially, respectively. Also, by decreasing the oxide thickness, SNM and power consumption are increased; however, the delay behaves differently with chiralities (6,0) and (10,0). This research demonstrates the importance of accurately determining the GNRFET adjustable parameters according to the design aims. A set of recommendations is provided for optimal parameters needed by digital circuit designers to use GNRFET in their design optimally.

Patterning Graphene Films by H2O-Based Magnetic-Assisted UV Photolysis.

Properly cutting graphene into certain high-quality micro-/nanoscale structures in a cost-effective way has a critical role. Here, we report a novel approach to pattern graphene films by H2O-based magnetic-assisted ultraviolet (UV) photolysis under irradiation at 184.9 nm. By virtue of the paramagnetic characteristic, the photo-dissociated hydroxyl [OH(X2Π)] radicals are magnetized and have their oxidation capability highly enhanced through converting into an accelerated directional motion. Meanwhile, the precursor of H2O(X̃1A1) molecules distributes uniformly thanks to its weak diamagnetic characteristic, and there exists no instable diamagnetic intermediate to cause lateral oxidation. Possessing these unique traits, the H2O-based magnetic-assisted UV photolysis has the capability of making graphene microscale patterns with the linewidth down to 8.5 μm under a copper grid shadow mask. Furthermore, it is feasible to pattern graphene films into 40 nm-wide ribbons under ZnO nanowires and realize hybrid graphene/ZnO nanoribbon field-effect transistors with a hole mobility up to 7200 cm2·V-1·s-1. The X-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry analyses reveal that OH(X2Π) radicals act as a strong oxidant and that another product of H(12S) adsorbs weakly on graphene.

High-Mobility, Low-Temperature, CMOS Back-End Compatible III-V Crystalline Material Growth

In this work, we present a low temperature templated liquid phase (LT-TLP) growth process, that enables us to directly grow high optoelectronic quality single crystalline compound semiconductors on amorphous dielectrics at temperatures below 400 0C. Importantly, we show that when compared to other non-epitaxial growth techniques, this approach results in materials which exhibit 1-2 orders of magnitude improved mobility. This is attributed to the ability to grow single crystalline materials in desired geometries, removing the polycrystalline interfaces which dramatically degrade mobility of most crystalline materials. We demonstrate both InP and InAs, and interestingly observe a peak in quality when InP is grown at 300 oC, a temperature which is low enough to enable back-end-of-line growth on fully fabricated Si CMOS circuits. Using this low-temperature grown InP, we then develop a transistor fabrication process entirely carried out at 300 oC or below and demonstrate an indium phosphide nanoribbon field effect transistor with excellent on/off ratios, indicating low defect density in the material. Additionally, we demonstrate high electron mobility single crystal InAs mesas monolithically integrated on amorphous dielectric substrates at a growth temperature of 300°C. Critically, a room temperature mobility of ~5800 cm2/V-s was measured, the highest mobility reported for any thin-film semiconductor material system directly grown on a non-epitaxial substrate. Detailed modeling of the scattering mechanisms in the grown material indicates that the mobility is limited by surface roughness scattering, not the intrinsic material quality. We project that reducing the RMS surface roughness of the InAs from 1.8 nm to 1 nm would produce materials with room temperature mobilities of >10,000 cm2/V-s, and RMS roughness of 0.5 nm would result in mobility ~20,000 cm2/V-s, essentially identical to epitaxially grown materials. These results pave the way for growth of high-mobility materials directly onto the back-end of silicon CMOS wafers as well as other non-epitaxial substrates such as glass, and polymers for flexible electronics. Figure 1

Sub-10 nm patterning of few-layer MoS2 and MoSe2 nanolectronic devices by oxidation scanning probe lithography

The properties of 2D materials devices are very sensitive to the physical, chemical and structural interactions that might happen during processing. Low-invasive patterning methods are required to fabricate devices at the nanoscale. Here we developed a process that combines oxidation scanning probe lithography (o-SPL) and oxygen plasma to fabricate nanoribbon field-effect transistors and nano-constrictions on few-layer MoS2 and MoSe2. The oxygen plasma has a double role in this process. First, it forms a thin, uniform oxide layer on top of the flake surface to enable o-SPL nanopatterning with full control of shape and size. Second, the oxide layer thins down the flake. Both plasma-based and o-SPL oxides are soluble in deionized H2O, which enabled etching and the definition of electrically isolated nano-constrictions and nanoribbons. The accuracy and robustness of the process was applied to pattern sub-10 nm wide constrictions and nanoribbon transistors.

Design of ternary logic gates and circuits using GNRFETs

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Effects of Channel Dimension and Doping Concentration of Source and Drain Contacts on GNRFET Performance

Growth of the electronic industry has been accompanied by the increasing number of components on a chip. Consequently, it is necessary to shrink device dimension. In this paper, effects of channel dimension reducing of the graphene nanoribbon field effect transistors (GNRFET) on performance of the GNRFET are studied. Also, effects of increasing in source/drain contacts doping concentration of the GNRFET are discussed. In order to device simulation, non-equilibrium Green’s function (NEGF) equation is applied for self-consistent solving of Poisson and Schrodinger equations with the tight binding approximation in the mode space and ballistic regime. According to the simulation results, channel length reduction of the GNRFET causes higher values in ON-state and OFF-state currents, transconductance (gm), subthreshold swing and drain induced barrier lowering (DIBL). Also, it causes lower values in threshold voltage and ION/IOFF ratio. Decreasing in channel width of the GNRFET, causes lower values in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes higher values in ION/IOFF ratio and threshold voltage. Increasing in source/drain contacts doping concentration of the GNRFET causes increasing in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes decreasing in ION/IOFF ratio and threshold voltage. The effects of channel dimension reducing and contacts doping concentration on the transistor performance should be considered for optimal design, fabrication and selection of GNRFETs in various circuits and applications.

Flexible Multiplexed In2O3 Nanoribbon Aptamer-Field-Effect Transistors for Biosensing.

SummaryFlexible sensors are essential for advancing implantable and wearable bioelectronics toward monitoring chemical signals within and on the body. Developing biosensors for monitoring multiple neurotransmitters in real time represents a key in vivo application that will increase understanding of information encoded in brain neurochemical fluxes. Here, arrays of devices having multiple In2O3 nanoribbon field-effect transistors (FETs) were fabricated on 1.4-μm-thick polyethylene terephthalate (PET) substrates using shadow mask patterning techniques. Thin PET-FET devices withstood crumpling and bending such that stable transistor performance with high mobility was maintained over >100 bending cycles. Real-time detection of the small-molecule neurotransmitters serotonin and dopamine was achieved by immobilizing recently identified high-affinity nucleic-acid aptamers on individual In2O3 nanoribbon devices. Limits of detection were 10 fM for serotonin and dopamine with detection ranges spanning eight orders of magnitude. Simultaneous sensing of temperature, pH, serotonin, and dopamine enabled integration of physiological and neurochemical data from individual bioelectronic devices.

Improving the performance of graphene nanoribbon field-effect transistors by using lanthanum aluminate as the gate dielectric

In nanoscale transistors, electron tunneling increases and causes a large leakage current due to the reduced channel length and gate oxide thickness. To reduce the short-channel effects and leakage current, the gate oxide can be selected from materials with high dielectric constant. In this paper, lanthanum aluminate (LaAlO3), a material with a high dielectric coefficient, is used as a gate dielectric in the structure of graphene nanoribbon field-effect transistors (GNRFET) and the effect of using this material on the device performance is studied. The transistor characteristics are extracted from device simulations performed by self-consistently solving the Poisson and Schrodinger equations in the nonequilibrium Green’s function formalism, employing the tight-binding approximation in the mode-space and ballistic regime. The ON-state and OFF-state currents, the ION/IOFF ratio, the threshold voltage, the drain-induced barrier lowering (DIBL), the subthreshold swing, and the transconductance (gm) are calculated for LaAlO3 as well as different materials as the gate dielectric to investigate the device performance. Based on the simulation results, the use of LaAlO3 as the gate dielectric in the transistor structure instead of other materials leads to larger values of the ON-state current, ION/IOFF ratio, and gm as well as smaller values of the OFF-state current, threshold voltage, DIBL, and subthreshold swing. According to the obtained results and excellent properties of LaAlO3, the use of this material could improve the performance of GNRFETs.

The Parametric Study of Armchair Graphene Nanoribbon Field Effect Transistor by Non-Equilibrium Green's Function Method.

We have carried out a comprehensive parametric analysis on the potential performance of a graphene nanoribbon field effect transistor (GNRFET). We modeled the behavior of GNRFETs with nanometer width GNR channels to formulate a self-consistent, non-equilibrium Green's function (NEGF) scheme in conjunction with the Poisson equation and allow the GNRFET to operate as a switch. Based on the results, we propose a metric to compete with current silicon CMOS highperformance (HP) or low-power (LP) devices, explaining that this can vary widely depending on the GNRFET structure parameters.

An ultra-low-power and high-performance SRAM cell design based on GNRFETs

ABSTRACT In this letter, we propose a new design of an ultra-low-power and high performance six – transistor (6 T) static random access memory (SRAM) cell using graphene nanoribbon field-effect transistors (GNRFETs). HSPICE (Simulation Program with Integrated Circuit Emphasis)-compatible compact GNRFETs model is used to design and validate the different SRAM cells. The proposed cell improves the performance in terms of power consumption, read data stability, and writeability at the low supply voltage. The proposed cell also significantly reduces the leakage power consumption due to excellent control on the gate leakage current. The small bandgap and the high ratio in a GNRFET device show great potential for high-speed nanoelectronics applications. The cell consumes ultra-low power due to its capability to operate below 0.5 V, which makes it suitable for low power applications.

Low Power based Dynamic TSPC D flip flop for High Performance Applications

D flip-flop is viewed as the most basic memory cell in by far most of computerized circuits, which brings it broad usage, particularly under current conditions where high-thickness pipeline innovation is as often as possible utilized in advanced coordinated circuits and flip-flop modules are key segments. As a constant research center, various sorts of zero flip-flops have been concocted and explored, and the ongoing exploration pattern has gone to rapid low-control execution, which can be come down to low power-defer item. To actualize superior VLSI, picking the most proper D flip-flop has clearly become an incredibly huge part in the structure stream. The quick headway in semiconductor innovation made it practicable to coordinate entire electronic framework on a solitary chip. CMOS innovation is the most doable semiconductor innovation yet it neglects to proceed according to desires past and at 32nm innovation hub because of the short channel impacts. GNRFET is Graphene Nano Ribbon Field Effect Transistor, it is seen that GNRFET is a promising substitute for low force application for its better grasp over the channel. In this paper, an audit on Dynamic Flip Flop and GNRFET is introduced. The power is improved in the proposed circuit for the D flip flop TSPC.

DNA sequencing via Z-shaped graphene nano ribbon field effect transistor decorated with nanoparticles using first-principle transport simulations

DNA detection has revolutionized medical and biological research fields. It provides a wealth of medical information for each individual, which can be used in a personalized medicinal procedure in the future. Genome sequence helps to enhance our perception of inheritance, disease, and individuality. This work aims to improve DNA sequencing accuracy and the overall current signal using a novel nano pore based sensor that is developed to detect and identify the DNA bases. Herein, a novel z-shaped field effect transistor with a nano pore for the aim of DNA detection is studied, where a gate terminal is added below the center of the z-shaped graphene nano ribbon. First-principle transport calculations are used to identify the DNA bases and electronic signature. An efficient density functional theory approach combined with non-equilibrium Green’s function formalism (DFT + NEGF) are utilized to detect the transmission spectrum and current for DNA nucleo bases: Adenine, Thymine, Guanine, and Cytosine. Using transmission current, a distinctive electronic signature is generated for each DNA base to detect each DNA sequence. Various orientations and lateral position for each DNA base are considered. Moreover, the effect of decorating the developed DNA sensor with gold and silver nanoparticles on the sensor’s electrical current and transmission spectra is studied and analyzed. The results suggest that the z-shaped sensor could achieve DNA sequencing with high accuracy. The practical implementation of this work represents the capability to anticipate and cure diseases from the genetic makeup perspective.

Low Temperature Growth of Crystalline Semiconductors on Nonepitaxial Substrates

AbstractIn this work, a low temperature templated liquid phase (LT‐TLP) growth process is presented, that enables one to directly grow high optoelectronic quality single crystalline compound semiconductors (InP and InAs) on amorphous dielectrics at temperatures below 400 °C. Uniquely, the material quality is optimal when InP is grown at 300 °C, a temperature which is low enough to enable back‐end‐of‐line growth on fully fabricated Si complementary metal oxide semiconductor circuits. Using this low‐temperature grown InP, a transistor fabrication process is then entirely carried out at 300 °C or below, and an indium phosphide nanoribbon field effect transistor with excellent on/off ratios is demonstrated, indicating low defect density in the material. Overall, this approach enables growth of large area (tens of micron) single crystal compound semiconductor at low temperatures, establishing a back‐end‐of‐line (BEOL) compatible process for monolithic 3D device integration.

Stability Improvement of an Efficient Graphene Nanoribbon Field-Effect Transistor-Based SRAM Design

The development of the nanoelectronics semiconductor devices leads to the shrinking of transistors channel into nanometer dimension. However, there are obstacles that appear with downscaling of the transistors primarily various short-channel effects. Graphene nanoribbon field-effect transistor (GNRFET) is an emerging technology that can potentially solve the issues of the conventional planar MOSFET imposed by quantum mechanical (QM) effects. GNRFET can also be used as static random-access memory (SRAM) circuit design due to its remarkable electronic properties. For high-speed operation, SRAM cells are more reliable and faster to be effectively utilized as memory cache. The transistor sizing constraint affects conventional 6T SRAM in a trade-off in access and write stability. This paper investigates on the stability performance in retention, access, and write mode of 15 nm GNRFET-based 6T and 8T SRAM cells with that of 16 nm FinFET and 16 nm MOSFET. The design and simulation of the SRAM model are simulated in synopsys HSPICE. GNRFET, FinFET, and MOSFET 8T SRAM cells give better performance in static noise margin (SNM) and power consumption than 6T SRAM cells. The simulation results reveal that the GNRFET, FinFET, and MOSFET-based 8T SRAM cells improved access static noise margin considerably by 58.1%, 28%, and 20.5%, respectively, as well as average power consumption significantly by 97.27%, 99.05%, and 83.3%, respectively, to the GNRFET, FinFET, and MOSFET-based 6T SRAM design.