Nanoelectromechanical Relays Research Articles

Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs

Multi-Gate In-Plane Actuated NEMS Relays for Effective Complementary Logic Gate Designs

Integrated 4-terminal single-contact nanoelectromechanical relays implemented in a silicon-on-insulator foundry process.

Integrated nanoelectromechanical (NEM) relays can be used instead of transistors to implement ultra-low power logic circuits, due to their abrupt turn off characteristics and zero off-state leakage. Further, realizing circuits with 4-terminal (4-T) NEM relays enables significant reduction in circuit device count compared to conventional transistor circuits. For practical 4-T NEM circuits, however, the relays need to be miniaturized and integrated with high-density back-end-of-line (BEOL) interconnects, which is challenging and has not been realized to date. Here, we present electrostatically actuated silicon 4-T NEM relays that are integrated with multi-layer BEOL metal interconnects, implemented using a commercial silicon-on-insulator (SOI) foundry process. We demonstrate 4-T switching and the use of body-biasing to reduce pull-in voltage of a relay with a 300 nm airgap, from 15.8 V to 7.8 V, consistent with predictions of the finite-element model. Our 4-T NEM relay technology enables new possibilities for realizing NEM-based circuits for applications demanding harsh environment computation and zero standby power, in industries such as automotive, Internet-of-Things, and aerospace.

3-D coarse-grained reconfigurable array using multi-pole NEM relays for programmable routing

We propose the use of multi-pole nanoelectromechanical (NEM) relays for routing multi-bit signals within a coarse-grained reconfigurable array (CGRA). We describe a CMOS-compatible multi-pole relay design that can be integrated in 3-D and improves area utilization by 40% over a prior design. We then demonstrate a method for placing multiple contacts on a relay that can reduce contact resistance variation by 40× over a circular placement strategy. Additionally, we develop static and dynamic SPICE models (calibrated to accurate finite element models) for predicting circuit-level performance with these devices. Finally, we establish a methodology for integrating these relays into an industry-standard digital design flow. Using our multi-pole relay design, we perform post-layout simulation of a hybrid CMOS-NEMS CGRA processing element (PE) tile in 40 nm technology. We achieve up to 19% lower area and 10% lower power at iso-delay, compared to a CMOS-only CGRA PE tile. The results show a way to bridge the performance gap between programmable logic devices (such as CGRAs) and application-specific integrated circuits using NEMS technology.

Theory, Design, and Characterization of Nanoelectromechanical Relays for Stiction-Based Non-Volatile Memory

Diverse areas such as the Internet of Things (IoT), aerospace and industrial electronics increasingly require non-volatile memory to work under high-temperature, radiation-hard conditions, with zero standby power. Nanoelectromechanical (NEM) relays uniquely have the potential to work at 300 °C and absorb high levels of radiation, with zero leakage current across the entire operational range. While NEM relays that utilise stiction for non-volatile operation have been demonstrated, it is not clear how to design a relay to reliably achieve given programming and reprogramming voltages, an essential requirement in producing a memory. Here, we develop an analytical, first-principle physics-based model of rotational NEM relays to provide detailed understanding of how the programming and reprogramming voltages vary based on the device dimensions and surface adhesion force. We then carry out an experimental parametric study of relays with a critical dimension of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~\mathrm {80~~\, \text {n} \text {m} }$ </tex-math></inline-formula> to characterise the surface adhesion force, and derive guidelines for how a NEM relay should be dimensioned for a given contact surface force, feature size constraints and operating requirements. We carry out a scaling study to show that voltages of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~\mathrm {1~~\, \text {V}}$ </tex-math></inline-formula> and a footprint under <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~\mathrm {2~~\, \mu \text {m} ^{2}}$ </tex-math></inline-formula> can be achieved with a critical dimension of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\approx ~\mathrm {10~~\, \text {n} \text {m} }$ </tex-math></inline-formula> , with this device architecture. [2021-0138]

DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays

Ternary content addressable memory (TCAM) is one type of associative memory and has been widely used in caches, routers, and many other mapping-aware applications. While the conventional SRAM-based TCAM is high speed and bulky, there have been denser but slower and less reliable nonvolatile TCAMs using nonvolatile memory (NVM) devices. Meanwhile, some CMOS TCAMs using dynamic memories have been also proposed. Although dynamic TCAM could be denser than the 16T SRAM TCAM and more reliable than the nonvolatile TCAMs, CMOS dynamic TCAMs still suffer from the row-by-row refresh energy and time overheads. In this article, we propose dynamic TCAM using nanoelectromechanical (NEM) relays (DyTAN), and utilize one-shot refresh (OSR) to solve the memory refresh problem. By exploiting the unique NEM relay characteristics, DyTAN outperforms the existing works in the balance between density, speed, and power efficiency. Compared with the 16T SRAM-based TCAM, the 5T CMOS dynamic TCAM, the 2T2R TCAM, and the 2FeFET TCAM, evaluations show that the proposed DyTAN reduces the write energy by up to $2.3\times $ , $1.3\times $ , $131\times $ , and $13.5\times $ , and improves the search energy-delay-product (EDP) by up to $12.7\times $ , $1.7\times $ , $1.3\times $ , and $2.8\times $ , respectively.

Electrical Characteristics of Nanoelectromechanical Relay with Multi-Domain HfO2-Based Ferroelectric Materials

Since the discovery of ferroelectricity in HfO2-based materials which are comparable to the complementary metal-oxide–semiconductor (CMOS) fabrication process—a negative capacitance effect in the HfO2-based materials has been actively studied. Owing to nonuniform polarization-switching (which is originated from the polycrystalline structures of HfO2-based ferroelectric materials), the formation of multi-domains in the HfO2-based materials is inevitable. In previous studies, perovskite-based ferroelectric materials (which is not compatible to CMOS fabrication process) were utilized to improve the electrical properties of a nanoelectromechanical (NEM) relay. In this study, the effects of a multi-domain HfO2-based ferroelectric material on the electrical characteristics of an NEM relay were theoretically examined. Specifically, the number of domains, domain inhomogeneity and ferroelectric thickness of the multi-domain ferroelectric material were modulated and subsequently, its corresponding results were discussed. It was observed that the switching voltage variation was decreased with increasing the number of domains and decreasing domain inhomogeneity. In addition, the switching voltage was decreased with increasing ferroelectric thickness, owing to enhanced voltage amplification.

Modeling and design of an ultra low-power NEMS relays: application to logic gate inverters

In this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of the electrostatic force and the ohmic contact of the nanobeams’ tip with the fixed output electrode. The derived electromechanical model is used for electrical and energy analysis. Simulations are used to confirm the functionality of the inverter. The analysis of the switching energy showed very low power consumption compared to classical CMOS inverters. It is shown that the proposed inverter dissipates only 0.45 fJ to code a “1” logic-state and 0.023 fJ to code a “0” logic-state.

One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories

This brief presents the concept of one-shot refresh (OSR) for dynamic memories. The uniqueness of OSR that differs from the conventional row-by-row refresh operations, is that OSR is able to refresh all rows in the entire array by just one single refresh without the need to read out the stored data in each row. By doing so, significant energy savings could be achieved, and the time window accessible for regular read and write operations is widened with less disruption by the refresh traffic. We show that a few devices could be used to update existing designs to gain the OSR capability. These devices all exhibit hysteretic I-V characteristics and support the OSR data-independent refresh without the need to read out data first. The enabler is the proposed circuit technique for refresh and standby. As a proof of concept, we showcase an OSR-enabled embedded dynamic random-access memory (eDRAM) using the nano-electromechanical (NEM) relay, a type of CMOS-compatible device. Comparative evaluations show the merits of OSR more thoroughly.

Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory

Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 ∘C.

Reducing adhesion energy of nano-electro-mechanical relay contacts by self-assembled Perfluoro (2,3-Dimethylbutan-2-ol) coating

To enable energy-efficient electronic devices for the future, nano-electro-mechanical (NEM) relays are promising due to their high ON/OFF current ratio and potential for low operating voltage. To minimize hysteresis and, consequently, relay operating voltage, it is imperative to reduce the relay contact adhesion, which can be achieved by coating the contacts with anti-stiction self-assembled monolayers. Herein we report a 71% reduction in hysteresis voltage by utilizing a branched perfluorocarbon antistiction molecule: Perfluoro (2,3-Dimethylbutan-2-ol) (PDB) on top of the tungsten contact surfaces. Experimental results show the operation of a PDB-coated NEM relay with abrupt switching, undetectably low OFF-state current, hysteresis voltage as low as 20 mV, and a large ON/OFF current ratio (&amp;gt;107).

Impact of negative capacitance on the energy-delay property of an electromechanical relay

The energy-delay characteristics of a nanoelectromechanical (NEM) relay can be improved incomparably by using negative capacitance (NC) in a ferroelectric capacitor. This can augment the internal voltage of a device, which is larger than the externally applied voltage. In this study, the energy-delay product of an NC + NEM relay (in which the ferroelectric capacitor is connected to a switching electrode of an NEM relay in series), as well as the adhesion force of the relay, is investigated. The enhanced energy-delay property of an NEM relay is demonstrated theoretically.

Ferroelectric-Gated Nanoelectromechanical Nonvolatile Memory Cell

A ferroelectric-gated nanoelectromechanical (NEM) nonvolatile random-access memory cell [negative capacitance (NC)-NEM memory] is proposed and investigated. By adjusting the structural parameters of the NEM relay, the pull-in voltage of the NC-NEM memory cell can be reduced, and its pull-out voltage can even become negative. Hence, an NEM relay with a ferroelectric layer in the gate stack can be used as a nonvolatile random-access memory cell. Herein, the device design and operational principles for read/program/erase are introduced in detail. The program/erase voltage and the program delay time of the NC-NEM memory cell have been quantitatively estimated.

Simulation Techniques for Nanoelectromechanical (NEM) Relay.

Nanoelectromechanical (NEM) relays have been studied for use in low-power logic applications because of their conspicuous features of (i) zero off-state leakage and (ii) abrupt on/off switching behavior in principle. In this study, a lateral NEM relay is analytically modeled. Then, the pull-in/out voltages, which work as turn-on/off voltages for the device, are estimated quantitatively using equations that explain the operational principle of the NEM relay. Exemplary design parameters are proposed to ensure the operation of the NEM relay as a logic device, and its transfer characteristics are analyzed.

Nano-crystalline graphite for reliability improvement in MEM relay contacts

Micro- and Nano-electromechanical (MEM/NEM) relays can operate with zero-leakage at far higher temperatures and levels of radiation than transistors, but have poor reliability. This work demonstrates improvement in reliability of MEM relays using nano-crystalline graphite (NCG)-coated contact surfaces. The high stability of NCG in ambient air, along with its low surface energy, appears to make it an ideal contact material. NCG-coated relays achieved over 2.8 million fast, hot-switching cycles with a drain current of at least 5 μA and on-resistance under 17 kΩ, in ambient air. The relays also were tested in slow, hot-switching cycles designed to increase the electrical stress on the contact, and consistently achieved on-currents up to 50 μA or the imposed current limit without failure. The eventual cause of failure appeared to be mechanical stress on the NCG layer over repeated cycling causing degradation. Increasing the layer thickness is expected to further improve the contact reliability. The relays are scalable and can be used as micro- or nano-scale switches in electronic components designed for very high temperatures and levels of radiation.

Fabrication and characterization of a hammer-shaped CMOS/BEOL-embedded nanoelectromechanical (NEM) relay

This paper presents the results on the design, fabrication and characterization of a cantilever-type NEM relay featuring a hammer-shaped tip and built in the back end of a conventional 0.35μm CMOS technology. A high on/off current ratio (higher than 107), a subthreshold swing of only 285μV/dec, and zero off-state leakage current were experimentally observed. Through an endurance test of 3·103 switching cycles, the relay showed a stable pull-in voltage of 31.25V with an absolute variation of only 0.5V. The resonant frequency was also characterized, and observed at 456.97kHz. Finally, the paper discusses the usability of the presented device as a mass sensor with mass-stiffness decoupling capability for on-chip detection. This innovative feature, which could benefit the application portfolio of the emerging IoT era, lies on the fact that both pull-in voltage and resonant frequency can be fully electrically determined.

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 $\mu \text{m}$ , on-resistance of 200 $\text{k}\Omega$ , and a via pitch of 0.4 $\mu \text{m}$ , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to $15\times$ improvement in energy efficiency.

Design Issues for NEM-Relay-Based SRAM Devices

We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact model of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.

Macro-mechanics controls quantum mechanics: mechanically controllable quantum conductance switching of an electrochemically fabricated atomic-scale point contact

Here, we present a silver atomic-scale device fabricated and operated by a combined technique of electrochemical control (EC) and mechanically controllable break junction (MCBJ). With this EC-MCBJ technique, we can perform mechanically controllable bistable quantum conductance switching of a silver quantum point contact (QPC) in an electrochemical environment at room temperature. Furthermore, the silver QPC of the device can be controlled both mechanically and electrochemically, and the operating mode can be changed from ‘electrochemical’ to ‘mechanical’, which expands the operating mode for controlling QPCs. These experimental results offer the perspective that a silver QPC may be used as a contact for a nanoelectromechanical relay.

Adjusting the Operating Voltage of an Nanoelectromechanical Relay Using Negative Capacitance

The operating voltage of a nanoelectromechanical (NEM) relay can be scaled down significantly using negative capacitance (NC), which is a unique property of ferroelectric materials. It has been observed that a ferroelectric capacitor can amplify the internal voltage of a device (higher than the externally applied voltage) by means of the NC effect. In this simulation work, depending on the structural parameters of a ferroelectric capacitor and an NEM relay, an NC + NEM relay (in which the gate electrode of the NEM relay is connected in series to the ferroelectric capacitor) was investigated. As a result, a sub-0.5-V operating voltage is theoretically estimated.

Multi-Functional CMOS Compatible Nano-Electro-Mechanical Relays for Vapor Phase Explosive Detection

Nano-electro-mechanical (NEM) relays play a very important role in ultra-low standby power and ultra-low power vapor phase gas sensor for Internet-of-Things sensor applications. In this paper, for the first time, we demonstrate a multi-functional fully-CMOS compatible titanium-based NEM relay with 1.8V actuation voltage, ~100Ω R ON , 50ns turn ON delay, and 10 9 ON/OFF current ratio in the ambient conditions. The innovative feature of this paper lies on the novel combination of grayscale electron beam lithography and a bi-layer lift-off process at room temperature (RT) to realize an NEM relay. This novel combination facilitates easy release of structures with an air gap of 25nm and a beam size of 1μm × 1.5μm. As an example, using the proposed self-purging NEM relay, a vapor phase gas sensing application is successfully demonstrated for explosives detection in an ambient air at RT.