Abstract
The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 $\mu \text{m}$ , on-resistance of 200 $\text{k}\Omega$ , and a via pitch of 0.4 $\mu \text{m}$ , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to $15\times$ improvement in energy efficiency.
Highlights
Field programmable gate arrays (FPGA) are increasingly used in many high-value and safety-critical markets, as they significantly lower development and manufacturing costs and improve design productivity
While managing the contact reliability has been a major challenge, recent work has shown that using monocrystalline silicon relays with forms of carbon to act as a protective layer has potential to substantially improve the contact reliability [5], [6], opening up the possibility of realising reliable NEM relay-based FPGAs
NEM RELAY-BASED FPGAs we describe how complementary metal-oxide-semiconductor (CMOS)-only, hybrid NEMCMOS and NEM-only FPGAs are implemented for simulation
Summary
Field programmable gate arrays (FPGA) are increasingly used in many high-value and safety-critical markets, as they significantly lower development and manufacturing costs and improve design productivity. Despite the limitations of large footprint and high mechanical delay of NEM relays, Chen et al identified an opportunity to reduce energy and latency in FPGAs, by using the relays as programmable switches in the interconnection network in combination with CMOS circuits [14] They subsequently presented a simulation study to quantify performance improvements possible within a monolithic integration scheme [15]. The contributions of this paper are firstly in carrying out a comprehensive study based on via-last heterogeneous integration, which appears to hold out more promise to achieve reliable NEM-relay-based systems than monolithic integration It quantifies performance with on-resistance and scaled dimensions of integration pitch and relay footprint for NEM-only and NEM-CMOS systems, providing insight into how such systems can be designed under performance and energy constraints
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