Nanoelectromechanical Relays Research Articles

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal–oxide–semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy efficiency of the NEM relays despite their low switching endurance. This technique creates two virtual ground nodes in a block to allow: 1) a low power mode with functional NEM relays and 2) a normal mode with failed NEM relays. To demonstrate the applicability of this concept, we have applied it to a six-transistor SRAM cell as an illustrative example. We also investigate the applicability of this SRAM cell in field-programmable gate arrays and on-chip caches. Experimental results reveal that shadow NEM relays can reduce the power consumption of SRAM cells by up to 80% while addressing the limited switching endurance of NEM relays.

Study of electrical breakdown and secondary pull-in failure modes for NEM relays

In this work, two common failure modes of nano-electro-mechanical (NEM) relays: (1) electrical breakdown and (2) stiction due to secondary pull-in were analyzed. These effects are dominant when dimensions of the device are scaled to the sub-micrometer scale. Like MEMS devices, design adjustments, such as introduction of dimples, cannot provide a solution. The geometrical parameters and working environment drive directly the occurrence of these failure modes. The beam length is the key parameter in driving the electrical breakdown while the distance of the gate to the drain, the beam thickness, and the actuation gap set the limits for secondary pull-in voltage. The analysis shows that these failure modes could be mitigated and a physical parameters design space could be identified to achieve NEM devices for high speed operation.

Back-end-of-line compatible Poly-SiGe lateral nanoelectromechanical relays with multi-level interconnect

Nanoelectromechanical (NEM) relays show promise in a wide variety of low power applications. NEM relays have near-zero leakage current, in contrast to the relatively high leakage current of nanoscale CMOS transistors, thus enabling hybrid CMOS-NEM relay systems that are more energy efficient. If NEM relays can be fabricated in the back-end-of-line (BEOL) metallization process, they can be added to a CMOS integrated circuit without adding significantly to the die area. In this paper, we demonstrate a CMOS BEOL-compatible fabrication process of NEM relays with protected, buried interconnects. The NEM relay processing steps are at temperatures below 425 °C and all mechanical and chemical processing steps are designed to avoid damage to underlying CMOS transistors. We demonstrate a lateral relay with buried interconnect that switches for more than 1000 cycles with resistances below 300 kΩ in nitrogen at atmospheric pressure.

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology.

This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS) relays using a commercial complementary metal oxide semiconductor (CMOS) technology (ST 65 nm) following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V), good ION/IOFF (103) ratio, abrupt subthreshold swing (4.3 mV/decade) and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm). With these dimensions, the operable Cell area of the switch will be 3.5 μm (length) × 0.2 μm (100 nm width + 100 nm gap) = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

Process-Variation-Adaptive Charge Pump Circuit using NEM (Nano-Electro-Mechanical) Relays for Low Power Consumption and High Power Efficiency

For some low-frequency applications such as power-related circuits, NEM relays have been known to show better performance than MOSFETs. For example, in a step-down charge pump circuit, the NEM relays showed much smaller layout area and better energy efficiency than MOSFETs. However, severe process variations of NEM relays hinder them from being widely used in various low-frequency applications. To mitigate the process-variation problems of NEM relays, in this paper, a new NEMrelay charge pump circuit with the self-adjustment is proposed. By self-adjusting a pulse amplitude voltage according to process variations, the power consumption can be saved by 4.6%, compared to the conventional scheme without the self-adjustment. This power saving can also be helpful in improving the power efficiency of the proposed scheme. From the circuit simulation of NEM-relay charge pump circuit, the efficiency of the proposed scheme is improved better by 4.1% than the conventional.

The effect of device fabrication on quasi-static elastic behaviour of silicon nanocantilever arrays

As CMOS technology scaling continues, leakage current is increasingly degrading energy efficiency. The leakage problem can potentially be addressed by nanoelectromechanical (NEMS) relay technology, where the off state leakage current is virtually zero. These devices incorporate a suspended nanobeam which is drawn across a gap to make contact in similar fashion to a traditional relay. The properties of this nanobeam must be carefully engineered to minimise stiffness (hence operating voltage), while simultaneously maintaining sufficient restoring force to overcome the adhesion forces at the contact surface which are significant at the nanoscale. To engineer the beam stiffness, detailed understanding of the beam composition and geometry, combined with accurate modelling is required. Simple analytical models over-estimate the stiffness of the cantilever beam along its length, and both analytical and FEA models which account for the manufacturing induced geometrical complexity are required. In this work, spatial force mapping of fabricated beams was used to experimentally validate analytical and FEA models incorporating detailed beam dimensions. An excellent fit was achieved, and this provides a method for targeting beam properties in a NEMS device.

Partitioning Electrostatic and Mechanical Domains in Nanoelectromechanical Relays

This paper describes the improvement of pull-in stability, contact properties, and reliability of laterally actuated nanoelectromechanical relays by partitioning the mechanical and electrostatic domains in the relay structure. Separation of the two physics allows us to individually optimize the structural stiffness and the actuation voltage to increase the contact pressure and reduce the ON-state resistance without applying excessive drain voltage. The devices can tolerate more than 200% overdrive gate voltage, resulting in near 100% increase in contact force, and reducing the contact resistance from $\sim 10$ G $\Omega $ to $\sim 23$ K $\Omega $ . For a given overall device dimension, tailoring the mechanical and electrostatic elements independently also enables us to control the pull-in and pull-out voltages, which have different design requirements for different applications. The measurement results show that the pull-in/pull-out hysteresis could vary between 30% and 60% of the actuation (pull-in) voltage. Increasing the mechanical force without affecting the device actuation voltage improves the relay reliability by reducing the possibility of failure due to source–drain stiction when the relay is switched ON. As a proof of concept, mechanical relays are fabricated using polycrystalline silicon coated by a titanium nitride layer deposited via plasma enhanced atomic layer deposition. [2014-0018]

Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays

The application of nanoelectromechanical (NEM) memory switches to field-programmable gate arrays (FPGAs) has been proposed for the first time. NEM memory switches replace MOSFETs and NEM relay switches in connection blocks and switch boxes. The proposed NEM-memory-based FPGAs feature higher speed, lower energy consumption, and smaller chip area than the other FPGAs. In addition, compared with the previously reported NEM-relay-based FPGAs, they show nonvolatile storage of signal paths and stable rail-to-rail signal voltage swing because data signal paths are maintained by adhesion force. In addition, the contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {R} _{\rm co}$ </tex-math></inline-formula> ) of a NEM memory switch is lower than that of a NEM relay switch thanks to larger contact area.

Heterogeneous NEMS-CMOS DCM Buck Regulator for Improved Area and Enhanced Power Efficiency

In CMOS switches, the input signal modulates the on-channel resistance for a constant gate voltage. This necessitates over design of CMOS switches. Also, further CMOS scaling in the nanometer regime has failed to improve energy efficiency due to increasing leakage energy. Looking beyond CMOS, nanoelectromechanical (NEM) relays are a promising class of emerging devices that exhibit energy-efficient switching and zero leakage operation. $R_{\rm on}$ of the NEM relay switch is constant and is insensitive to the gate slew rate. This creates a paradigm shift in design of power switches. This coupled with infinite $R_{\rm off}$ offers significant area and power advantages over CMOS. Numerous end applications of NEM relay logic circuits have been proposed recently, including digital logic and memory. NEMS-based miniature switches form an interesting alternative in power management integrated circuits, the area of which is primarily dominated by CMOS power transistors. This study explores discontinuous-conduction mode buck regulator with specifications suitable for portable applications using a NEMS-CMOS hybrid design, and the results are compared against a standard commercial $0.35\hbox{-}{\rm \mu m}$ CMOS implementation. The electromechanical model has been developed for a suspended gate relay operating at 1 V with a nominal air gap of $5\hbox{--}10\; {\rm nm}$ published in the literature. The model accounts for the mechanical, electrical, and dispersion effects in the relay. This study shows that NEMS-CMOS hybrid dc–dc converter has an area savings of 60% over CMOS and achieves an overall higher efficiency over CMOS, with a peak efficiency of $94.3\%$ at $100 \;{\rm mA}$ .

Highly Scalable NEMS Relays With Stress-Tuned Switching Voltage Using Piezoelectric Buckling Actuators

This paper reports the design, fabrication, characterization, and scaling analysis of novel buckling-based nanoelectromechanical relays that use, for the first time, piezoelectric actuation. The generated stress from anchored piezoelectric films is employed to buckle a clamped-clamped beam to connect suspended source and drain terminals, while the residual stress in the beam is used to control the actuation voltage. This demonstration is the first of its kind to exploit residual stress to deliver a highly scalable switching mechanism that exhibits low actuation voltage (~1.8V), very fast switching (~80 ns), and uniquely achieves an equivalent electric body bias via mechanical methods. Finite-element analysis and analytical simulations show a linear dependence of the switching voltage on the residual stress, while the voltage versus stress tuning slope is reduced linearly with scaling the piezoelectric film thickness (-16.6 mV/MPa for 10-nm thick aluminum nitride film). A scaling analysis shows that millivolt switching is possible for aggressively miniaturized relays, which highlights the great impact this technology could have on demonstrating ultralow power digital circuits and memories.

Energy and Latency Optimization in NEM Relay-Based Digital Circuits

Digital circuits based on nanoelectromechanical (NEM) relays hold out the potential of providing an energy efficiency unachievable by conventional CMOS technology. This paper presents a detailed analysis of the operating characteristics of fabricated curved cantilever NEM relays using a comprehensive physical model. The mode of energy distribution within the electrical and mechanical operational domains of the relay is described in detail and the energy saving achievable by the technique of body-biasing is quantified. The analysis further reveals that the latency in a relay can be much larger or much smaller than the nominal mechanical delay depending on the point of actuation in the oscillation of the beam that takes place after pull-out. The methods that can utilize this phenomenon to reduce the latency of relay-based circuits are discussed, thus addressing one of the biggest challenges in NEM relay-based design.

Sub-1-volt Piezoelectric Nanoelectromechanical Relays With Millivolt Switching Capability

The design, fabrication, and characterization of the first piezoelectric nanoelectromechanical relays with sub-1-volt actuation (520 mV) are presented. The low actuation voltage is enabled by employing ultrathin piezoelectric aluminum nitride films (10 nm) with high c-axis orientation and controlled residual stress in a stress-compensating geometry. Two different actuation methods based on optimized four-layer unimorph actuators are used to synthesize normally closed relays with high mechanical restoring forces. The first experimental demonstration of few millivolts switching (10 mV) using the realized relays is also presented. The relays exhibit a very low energy dissipation per switching cycle (23 aJ), an extremely small subthreshold slope (0.013 mV/decade), and a low ON-state resistance (2.3 kQ).

NEM Relay-Based Sequential Logic Circuits for Low-Power Design

Nanoelectromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behaves like an ideal switch. The zero leakage operation has generated lot of interest in low power logic design using these relays [1],[2]. This paper presents various sequential circuit topologies using NEM relays and analyzes their power, performance, and area tradeoffs. The mechanical delay is inversely proportional to the gate-base voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> . This paper also presents an integrated voltage doubler-based flip-flop that improves the performance by 2× by overdriving V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gb</sub> . An electromechanical model which accounts for the mechanical, electrical, and dispersion effects of the suspended gate relay operating at 1 V with a nominal air gap of 5-10 nm has been developed based on published fabrication results in . Three sequential logic benchmark circuits were designed using NEM relays to verify the correctness of operation of the proposed circuits. This study explores different relay-based latch and flip-flop topologies, proposes fast sequential circuits that can operate at a frequency of 1/2t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> (theoretical fastest frequency for NEM relay logic circuits) and further improves speed of sequential circuits by distributed charge boosting.

Laterally Actuated Platinum-Coated Polysilicon NEM Relays

Laterally actuated polycrystalline silicon nanoelectromechanical (NEM) relays with enhanced electrical properties are presented. Due to surface oxidation of polysilicon in room ambient conditions, the relays have a high contact resistance (&amp;gt; 1 G&amp;#x03A9;) that requires high drain bias (3-5 V) to break through. The addition of a platinum sidewall coating reduces the on-resistance and the required drain bias to as low as 3 k&amp;#x03A9; and 0.1 V, respectively. The platinum coating's stability is demonstrated by two tests: first, a contact-and-hold test where the relay passes current (~1&amp;#x03BC;A) for up to 155 min and, second, a hot cycling test where the relay survives for over 108cycles . The NEMS relays are simulated using finite-element analysis, and the models are verified against experimental tests. Furthermore, the relays are configured and tested as a 2 : 1 multiplexer to show their potential as a digital logic component.

微纳机电系统(MEMS/NEMS)前沿

The micro-nanoelectromechanical systems (MEMS/NEMS, herein called MEMS for simplicity), which the originate from microelectronics technology, can deal with the thermal, optical, magnetic, chemical, and biological variables. Various structures and devices can be fabricated on a chip through the integration technology. In the last few decades, MEMS has played increasingly important roles in aerospace, military, optical communication, wireless communication, biomedicine, etc., and MEMS products have been widely used in our daily lives. Due to the highly multidisciplinary nature, MEMS shows a diverse research and development trend. This report will discuss the status and trend of the development of MEMS fundamental research. The discussion will focus on the fusion of MEMS technology with integrated circuits, nanotechnology, and modern biotechnology. The strong intervention of the TSMC, the largest IC foundry in the world, in MEMS foundry industry greatly accelerates the pace of integration of MEMS and IC. More and more new nano-materials and nanofabrication technologies have been applied in MEMS technology to promote the performance and the emergence of new devices. On the other hand, NEMS technology provides new nanoscale three-dimensional processing approaches for novel CMOS devices, and spawns new types of IC devices, such as NEMS relays and nano-mechanical memories. The combination with the biotechnology becomes a new growth point of MEMS, where the exible electrode and circuit is one of the typical representatives.

Integration of Nanoelectromechanical Relays With Silicon nMOS

Electrostatically actuated nanoelectromechanical (NEM) relays are integrated with silicon nMOS devices. An nMOSFET successfully drives a NEM relay with the MOSFET serving as a pass transistor to control the state of the relay. Silicon MOSFET-NEM relay integration opens up the possibility for applications, where the zero off-state leakage, the sharp on/off transition, and/or the hysteresis of the NEM relay can be used to complement the capabilities of CMOS.

Analog Nanoelectromechanical Relay With Tunable Transconductance

We show by simulation that a three-terminal nanoelectromechanical (NEM) relay combined with a feedback resistor provides a tunable transconductance Gm over an adjustable input-voltage range. The Gm arises from the modulation of the drain tunneling current by the gate voltage and does not require mechanical contact between the cantilever tip and the drain electrode. The introduced analog relay featuring current-voltage characteristics that are very similar to those of electronic transistors paves the path for purely electromechanical systems, where sensors and actuators can be integrated with NEM analog circuits and emerging NEM logic and memory devices.

Theoretical and experimental investigations of three-terminal carbon nanotube relays

We present theoretical and experimental investigations of three-terminal nanoelectromechanical relays based on suspended carbon nanotubes. A charge is induced in the nanotube by applying a voltage to an underlying gate electrode thus inducing the nanotube to bend and make contact with a drain electrode. Such devices have potential applications as fast switches, logic devices, memory elements and pulse generators. We describe two modes of operation: a contact mode where the nanotube makes physical contact with the drain electrode and a non-contact mode where electrical contact between the nanotube and the drain electrode is made via a field emission current.

High frequency properties of a CNT-based nanorelay

We have theoretically investigated the high frequency properties of a carbon-nanotube-basedthree-terminal nanoelectromechanical relay. The intrinsic mechanical frequency of the relayis in the GHz regime, and the electromechanical coupling shows a non-linear resonantbehaviour in this frequency range. We discuss how these resonances may be detected andshow that the resonance frequencies can be tuned by the bias voltage. Also, we show thatthe influence of external electromagnetic fields on the relay is negligible at all frequencies.