NAND Structure Research Articles

Selective Si<sub>3</sub>N<sub>4</sub> Etching for 3D NAND Integration by Using Low Concentration of H<sub>3</sub>PO<sub>4</sub>

This study investigated the etching kinetics of Si3N4 in various concentration of H3PO4 solution and the effect of Si3N4 etching enhancers on the etching process, particularly for 3D NAND trench structures. 30 wt% H3PO4 was used to etch Si3N4, which can produce higher Si3N4/SiO2 etching selectivity and similar Si3N4 etching rate compared to a conventional 85 wt% H3PO4. 30 wt% H3PO4 showed significantly improved etching performance for the Si3N4/SiO2 3D NAND structure as compared to 85 wt% H3PO4. In particular, the transportation ability of H3PO4 into 3D NAND trench structures can be improved by reducing viscosity of etchant, which can be obtained by reducing the concentration of H3PO4. In addition, Si3N4 etching enhancers were introduced to accelerate the Si3N4 etching kinetics in 30 wt% H3PO4. Addition of such additives improved the Si3N4 etching rate and Si3N4/SiO2 etching selectivity while suppressing oxide regrowth. The results provide valuable insights for optimizing selective Si3N4 etching process in 3D NAND structures.

Investigation of Oxide Regrowth in the Selective Si<sub>3</sub>N<sub>4</sub> Etching Process for 3D NAND Fabrication by Using Finite Element Modeling Simulation

In the process of manufacturing three-dimensional Not AND (3D NAND) flash memory devices, oxide regrowth occurs during the selective Si3N4 etching process on the Si3N4/SiO2 multi-stack structures. The oxide regrowth issue must be suppressed. Thus, effects of two factors, the mass transfer ability of etching byproduct and the stack number of 3D NAND structure, on oxide regrowth were investigated in this study using finite element method (FEM) simulation. Using FEM simulation, we predicted that increase in the stack number of the 3D NAND structure and decrease in the diffusivity of Si3N4 etching byproducts highly aggravated the oxide regrowth. Therefore, it was suggested that an etchant capable of promoting H2SiO3 diffusion behavior would inhibit the oxide regrowth during the selective Si3N4 etching process of the 3D NAND structure.

A novel gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance with disturbance-less program operation

In this paper, we propose a gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance and reliability. First, in the selected string, we confirmed that the proposed structure can improve program performance using negative bit-line voltage scheme with pass disturbance-less characteristic. Second, in the inhibited string, we confirmed self-boosting, which is perfectly performed by the back-gate bias without the unselected WL. Based on these potentials of the GAAB NAND structure, we would like to propose our GAAB structure as a future structure with the advantages of high performance and high reliability characteristics compared with conventional GAA-type NAND flash memory.

Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages.

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔVth) between the top cell and bottom cell in the same string. In detail, ΔVth between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔVth is affected is not very dependent on the stack height.

Understanding of Etching Mechanism of Si3N4 Film in H3PO4 Solution For The Fabrication of 3D NAND Devices

Silicon nitride (Si3N4) has been widely used as an insulating or etch stop layer in the semiconductor devices [1]. For example, in a 3D V-NAND flash memory manufacturing process, Si3N4 is alternately stacked with silicon oxide (SiO2) to form a NAND structure. Here, it is necessary to selectively etch Si3N4 avoiding etching of SiO2 in the repeated Si3N4/SiO2 multi-stack layers. In general, phosphoric acid (H3PO4) is used to selectively etch Si3N4 against SiO2 [2]. However, since the concentration of H3PO4 solution changes with the evaporation of H2O, it is not easy to determine the concentration dependence of Si3N4 etching rate in H3PO4 solution. In order to properly control the shape of the 3D V-NAND structure, it is necessary to extensively understand the effect of H3PO4 concentration on the Si3N4 etching. The study of Si3N4 etching has been mainly focused on the effect of additives in H3PO4 on the behavior of Si3N4 etching to solve the issue such as oxide regrowth so far [3, 4]. Fundamental study of the Si3N4 etching reaction mechanism in H3PO4 is lacking. In this study, the Si3N4 etching mechanism in H3PO4 solution is elucidated systematically.For the investigation of Si3N4 etching reaction mechanism, LPCVD Si3N4 blanket wafer and Si3N4/SiO2 multi-stack layered trench wafer were used. Etching experiments of of Si3N4 were conducted in 10-95 wt% H3PO4 solutions at 160 °C. Spectroscopic ellipsometry and field emission scanning electron microscopy were used to measure the etching rate of Si3N4 after etching process.First, the changes in etching rate of Si3N4 in the various concentrations of H3PO4 solution were investigated. As shown in Fig. 1, according to our kinetic calculation and experiments, etching rate of Si3N4 increased as the H3PO4 concentration increased until the concentration of H3PO4 reaches a certain concentration that produced the highest etching rate. However, etching rate of Si3N4 decreased with the concentration of H3PO4 beyond the critical H3PO4 concentration. According to the results, there may be two concentrations of H3PO4 solution which produce an identical etching rate of Si3N4. It is also suggested that not only H3PO4 but also H2O plays an important role in the Si3N4 etching kinetics.To investigate the role of H2O and H3PO4 in the etching reaction of Si3N4, kinetic isotope effect (KIE) of Si3N4 etching reaction in H3PO4 solution was used. KIE provides information about which reactant determines the rate-limiting step. In this study, each reactant of Si3N4 etching reaction, H2O or H3PO4, was substituted with D2O and D3PO4, respectively. Then, etching of Si3N4 was conducted in four different solutions. As shown in Fig. 2, when H3PO4 was replaced by D3PO4, the Si3N4 etching rate was not significantly changed. However, when H2O was replaced by D2O, the Si3N4 etching rate decreased by 30 %. Therefore, it is thought that rate-limiting step of the Si3N4 etching reaction is determined by an elementary reaction related to H2O rather than H3PO4.Based on the above results, Si3N4 etching reaction mechanism was suggested. First, the Si3N4 surface termination (-NH2) is substituted with H2PO4 -, which is a weak nucleophile, by an SN1-like reaction. When H2PO4 - binds to Si, the backbone of Si3N4 is weakened because the electronegativity of O (3.44) is greater than N (3.04). Next, the Si-N of the weakened backbone of Si3N4 is substituted with Si-OH by an SN2-like reaction of H2O. This SN2-like reaction is considered as a rate-limiting step. It is believed that understanding of etching mechanism of Si3N4 in H3PO4 solution will improve selective etching process of Si3N4 for the integration of 3D V-NAND.

A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration.

Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation

A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.

A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.

Thermal Isotropic Atomic Layer Etching of Metallic Molybdenum

In high aspect ratio structures such as 3D NAND stacks, high-k oxides or certain metals need to be removed from sidewalls and even non-line-of-site locations where access via reactive ion etching would be challenging or impossible. To achieve etching in these locations, thermal processes need to be applied that lack any intrinsic directionality and are therefore isotropic. Thermal Atomic Layer Etching is one option to facilitate this kind of process. Therefore, it has gathered significant attention recently and is now being explored in academia and industry.In this work, we demonstrate isotropic Atomic Layer Etching on metallic molybdenum using a three-step process that involves oxygenation of the metal surface, a conversion reaction using boron-trichloride followed by a hydrogen-fluoride clean step. We measured the etch rate per cycle to be around 10 Å with low temperature dependence in the range between 150°C and 250°C.Furthermore, we examined the effectiveness of various oxygenation methods on the surface of metallic molybdenum films. These methods included thermal oxygenation as a function of temperature, oxygenation by a remote plasma and in-situ plasma fluorination. We established that an oxygenation level of more than 70% as measured with XPS is needed in order for the ALE process to work. Levels in this range could be achieved via in-situ plasma oxygenation as well as with a remote plasma. Thermal oxygenation, on the other hand, required substrate temperatures in access of 400°C to oxygenate at the 70% level.In this study we also show an example of molybdenum ALE in an application that involved the removal of this metal from a 50:1 aspect ratio 3D NAND structure. We measured etch rates on vertical and horizontal surfaces as well as the depth dependence in removal rate of molybdenum.

A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory.

In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).

Effect of SiO2 Etching Inhibitor to H3PO4 for the Selective Si3N4 Wet Etching of 3D NAND

As the number of stacked layers of the 3D NAND structure increases, the memory density of 3D NAND flash memory device increases [1]. In the fabrication of 3D NAND device, it is essential to selectively etch Si3N4 by an etchant flowing along a narrow slit followed by metal deposition. However, as the number of Si3N4/SiO2 multi-stack increases, selective etching of Si3N4 becomes difficult. In order to increase the Si3N4-to-SiO2 etch selectivity, SiO2 etching inhibitor should be added to H3PO4. Unfortunately, most of SiO2 etching inhibitors added to H3PO4 generate oxide regrowth around SiO2 layer on the Si3N4/SiO2 multi-stack structure. In this study, the mechanism of oxide regrowth occurred on the 3D NAND structure was investigated. Patterned Si3N4/SiO2 multi-stack structures were prepared. Etching experiments were performed using coupon wafers in 85% H3PO4 or etching inhibitor-added H3PO4 at 160 °C. The Si3N4 and SiO2 etching rates and Si3N4-to-SiO2 etch selectivity were measured using spectroscopic ellipsometry and oxide regrowth on the Si3N4/SiO2 multi-stack structure was analyzed using FE-SEM and HR-TEM. When the Si3N4/SiO2 multi-stack structure was etched in the SiO2 etching inhibitor-added H3PO4, oxide regrowth was observed on the SiO2 layered trenches on the Si3N4/SiO2 multi-stack structure, as shown in Fig. 1. The oxide regrowth occurred intensively at the corner of SiO2 layered trench and oxide regrowth occurred heavily at the bottom of Si3N4/SiO2 multi-stack structure as compared to the top. The overall amount of oxide regrowth on the SiO2 layered trench increased as the concentration of SiO2 etching inhibitor added to H3PO4 increased. In addition, it is shown that generation rate of etching product is an important factor to occur oxide regrowth. Based on the results, it is suggested that etching inhibitor addition and high generation rate of etching product and mass transfer limitation are responsible for the oxide regrowth. Through their optimization, selective Si3N4 etching on the Si3N4/SiO2 multi-stack structure without oxide thinning and regrowth could be obtained, as shown in Fig. 2.

A novel horizontal channel NAND structure for vertically stacked type system LSI

A novel horizontal channel NAND structure for vertically stacked type system LSI

Etching of Silicon Nitride in 3D NAND Structures

3D NAND structures present a unique difficulty in semiconductor device manufacturing. One method of production consists of cylindrical structures made of alternating layers of silicon dioxide (SiO2) and silicon nitride (SiN) with a core of SiO2. As part of the device manufacturing process the SiN is etched away, leaving the SiO2 core with disc-shaped SiO2 fins. Due to material selectivity requirements of etching only the SiN while leaving the SiO2 unchanged, the process of choice is often immersion in a high-concentration hot phosphoric acid (H3PO4) bath with a silica additive to inhibit SiO2 etching, which with proper tuning can have selectivity of greater than 100:1 for etching SiN:SiO2. Like all wet etch processes, uniformity of the process is a constant concern. One of our goals in this paper is to show how we use experimental measurements and simulations to better understand what parameters have the most effect on the process, and how we can use that knowledge to improve the process. Experimentally we have measured the etch rate of blanket SiN and SiO2 wafers. We fit the etch rate data to Arrhenius models to quantify the etch rate of SiN and SiO2 films. Simulations of the etch process on both blanket wafers and patterned wafers showed that the etch rate is the same and doesn’t depend on feature geometry. In this paper we propose a simple chemical reaction and diffusion mechanism that explains the experimental observations of the etched structures. The uniformity of the SiN etching between the top and the bottom of the 3D NAND stacks indicates that the reaction rate is much slower than the rate of diffusion of reactants and products into and out of the structure, so the etching is a reaction-controlled mechanism. This indicates within-wafer uniformity and wafer-to-wafer uniformity variations as being primarily due to differences of temperature within the bath. We also conducted simulations of the etching of the SiN in the 3D NAND structure and the liquid flow in the bath to model and explain this mechanism. In these simulations we varied the rate of the surface reaction of H3PO4 etching SiN, and showed that for a fast reaction rate that the structure would etch from the top to the bottom as the overall reaction rate become diffusion limited, while for a slow reaction rate the entire structure would etch uniformly, showing it to be a reaction limited process. Another issue with SiN etching in an H3PO4 bath is that the etch rate of SiO2 depends highly on the concentration of silica, in fact the bath is generally pre-seeded with silica in order to achieve a lower SiO2 etch rate, though if above a critical concentration deposition is known to occur. Based on a study of silica chemistry, it may be possible for silica deposition to occur even when below the critical concentration. This would be a film that would grow on a SiO2 surface but would later dissolve back into solution. We propose a mechanism that explains the formation and later disappearance of the growth film on the SiO2 surface as a result of the etching of the SiN and the formation of silica byproducts into a sol/gel network. Sol/gels have the unique property of their ability to form in an area of locally high flux, and then later dissolve over a much longer time scale. The difference in forward and backward reaction rates of the sol/gel film formation and disillusion, respectively, are such that the system is never in equilibrium. Thus, even though all the silica can dissolve in the phosphoric acid at equilibrium, the silica formed from the SiN etching forms into a sol/gel polymer network that only slowly dissolves after SiN etching has stopped. We discuss the implications of this sol/gel oxide film for further process improvement. With better theoretical understanding of the SiN etching and possible silica sol/gel formation and dissolution process, we now have tools to better optimize the phosphoric acid bath, improving both etching uniformity and necessary process time. Figure 1

Design Technology of Stacked‐Type Chain PRAM

SUMMARYA stacked‐type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked‐type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low‐cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked‐type chain PRAM is a promising candidate for realizing high‐speed and low‐power future nonvolatile semiconductor memory.

Design Technology of Stacked Type Chain PRAM

SUMMARY A stacked-type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked-type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low-cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked-type chain PRAM is a promising candidate for realizing high-speed and low-power future nonvolatile semiconductor memory.

High-performance 1-Gb-NAND flash memory with 0.12-μm technology

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.

Reliability issues of flash memory cells

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 256 kbit ROM with serial ROM cell structure

The realization of a 256 kbit ROM using a 500 /spl Aring/ E/D NMOS technology is described. A high packaging density has been achieved by using a NAND structure in the memory array and in the decoders. Some characteristics of this serial ROM structure are discussed and compared with the conventional parallel configurations. The 32K/spl times/8 bit ROM with a bit size of 5.25/spl times/5.5 /spl mu/m/SUP 2/ has a total chip area of 18.6 mm/SUP 2/. Operating from a single 5 V supply, the device has a typical access time of 850 ns with a minimum cycle time of 1500 ns and dissipates 70 mW. In the power-down mode this power is reduced to 5 mW.