A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

Seonjun Choi,Changhwan Choi,Jae Kyeong Jeong,Myounggon Kang,Yun-Heub Song

doi:10.3390/electronics10010032

Seonjun Choi, Changhwan Choi + Show 3 more

Open Access

https://doi.org/10.3390/electronics10010032

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Abstract

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V.

Highlights

The recent development of NAND flash technology for high density has been extensively utilized in industry
This structure was employed as the virtual gate all (GAA) structure during device simulation through the cylindrical command (360 degree rotation) of the Sentaurus tool
An operation method of the proposed ferroelectric memory structure was proposed as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure and verified through device simulation

Summary

Introduction

The recent development of NAND flash technology for high density has been extensively utilized in industry. The most important difference is that the voltage that changes the threshold voltage of the memory cell in the positive direction is negative in the ferroelectric memory This means that the channel, not the word line, must have a positive voltage when the ferroelectric memory performs a program operation. Assuming multi-string operation, it is expected that selective program operation is not possible because all channels are always on in the proposed structure To solve this problem, in this paper, a new programming method using the BiCS (Bit Cost Scalable) GIDL (Gate Induce Drain Leakage) deletion method was proposed and verified through device simulation. Even in a multi-string operation, since it is possible to selectively generate GIDL only for the bit line (BL) to be programmed, the program operation is possible in the same manner as the existing V-NAND structure

Details of the Proposed Structure and Operation

Simulation Results and Discussion

Conclusions