Abstract
In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM).
Highlights
Since the advent of Moore’s Law, semiconductor performance has been improved
Compared to conventional 3D integrated-circuits (3DICs) based on through-silicon via (TSV), Monolithic 3DI (M3DI) can reduce the length of wiring because peach can be nano-scale and can be partitioned at the gate level to improve integrated circuit (IC) performance without relying on scaling [7]
The rising, fa7llionfg11 propagation delays, and power consumption of D flip-flop (D-FF) (TILD = 100 nm) without electrical couplingcaitraen1c2e.3anpds, r4e.s4isptsa,nacnedd3u9e.3toμWm,orneoslpitehcitcivienltye.rT-thieer rvisiain(gMaInVd) faanlldinmg eptraolpliangeat(iMonL)d.eWlahyesn ancidrcpuoitwseirmcuolnastiuomn potfiovnaroiof uDs-FloFg(iTcIcLDirc=ui1t0s nismp)ewrfoitrhmeeledc,tirticiaslnceocuepsslianrgytearbey1a5dpdsi,n5g.5epxtsr,a ancadp4a1c.i1taμnWce, arensdpreecstivstealny.ceCaocncosrideinrigntgotthhee eslteructcrtiucrael ocof ueapclihncgi,rcthueit rtiosionbgtaaindacfcaullriantge rpersouplatsg.ation delays, and power consumption increased by 21.9%, 22.7%, and 4.6%, respectively
Summary
Since the advent of Moore’s Law, semiconductor performance has been improved. silicon-based transistors below 10 nm have structural and physical fabrication challenges [1]. Various studies are underway to use 3DI in logic circuits [5,6]. Compared to conventional 3D integrated-circuits (3DICs) based on through-silicon via (TSV), M3DI can reduce the length of wiring because peach can be nano-scale and can be partitioned at the gate level to improve IC performance (such as, delay, power consumption, device density, frequency, and bandwidth) without relying on scaling [7]. Studies of 3D heterogeneous integration (e.g., complementary metal-oxide-semiconductor (CMOS) with nanoelectromechanical systems (NEMS), optical devices, or memory) that has been composed of CMOS and sensors or memory as a single stack have been reported [10,11,12]. In order to use M3DI in logic circuits, it is necessary. VFiguunriet c2esllhso, wiss1t0h0enpmro[p1o3s].eFdiglauyroeu2tsshanowd s3D stthruecpturorepsosoefdMla3yDoNutAs NanDda3nDdsMtru3cDtuNrOesRo.f M3DNAND and M3DNOR
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